Lines Matching +full:stm32 +full:- +full:dma
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/stm32/st,stm32-dma3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 DMA3 Controller
10 The STM32 DMA3 is a direct memory access controller with different features
16 GPDMA and HPDMA support 16 independent DMA channels, while only 4 for LPDMA.
17 GPDMA and HPDMA support 256 DMA requests from peripherals, 8 for LPDMA.
19 Bindings are generic for these 3 STM32 DMA3 configurations.
21 DMA clients connected to the STM32 DMA3 controller must use the format
22 described in "#dma-cells" property description below, using a three-cell
26 - Amelie Delaunay <amelie.delaunay@foss.st.com>
29 - $ref: /schemas/dma/dma-controller.yaml#
33 const: st,stm32mp25-dma3
42 Should contain all of the per-channel DMA interrupts in ascending order
43 with respect to the DMA channel index.
51 power-domains:
54 "#dma-cells":
57 Specifies the number of cells needed to provide DMA controller specific
60 The second cell is a 32-bit mask specifying the DMA channel requirements:
61 -bit 0-1: The priority level
66 -bit 4-7: The FIFO requirement for queuing source/destination transfers
72 The third cell is a 32-bit mask specifying the DMA transfer requirements:
73 -bit 0: The source incrementing burst
76 -bit 1: The source allocated port
79 -bit 4: The destination incrementing burst
82 -bit 5: The destination allocated port
85 -bit 8: The type of hardware request
88 -bit 9: The control mode
89 0x0: DMA controller control mode
91 -bit 12-13: The transfer complete event mode
101 - compatible
102 - reg
103 - interrupts
104 - clocks
105 - "#dma-cells"
110 - |
111 #include <dt-bindings/interrupt-controller/arm-gic.h>
112 #include <dt-bindings/clock/st,stm32mp25-rcc.h>
113 dma-controller@40400000 {
114 compatible = "st,stm32mp25-dma3";
133 #dma-cells = <3>;