Lines Matching +full:0 +full:x40026400

20           0x0: no address increment between transfers
21           0x1: increment address between transfers
23           0x0: no address increment between transfers
24           0x1: increment address between transfers
26           0x0: offset size is linked to the peripheral bus width
27           0x1: offset size is fixed to 4 (32-bit alignment)
29           0x0: low
30           0x1: medium
31           0x2: high
32           0x3: very high
34        -bit 0-1: DMA FIFO threshold selection
35          0x0: 1/4 full FIFO
36          0x1: 1/2 full FIFO
37          0x2: 3/4 full FIFO
38          0x3: full FIFO
40          0x0: FIFO mode with threshold selectable with bit 0-1
41          0x1: Direct mode: each DMA request immediately initiates a transfer
44          0x0: Use standard DMA ACK management, where ACK signal is maintained
46          0x1: Use alternative DMA ACK management, where ACK de-assertion does
104       reg = <0x40026400 0x400>;