Lines Matching +full:xlnx +full:- +full:zynqmp +full:- +full:dpdma
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/xlnx/xlnx,zynqmp-dpsub.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx ZynqMP DisplayPort Subsystem
10 The DisplayPort subsystem of Xilinx ZynqMP (Zynq UltraScale+ MPSoC)
14 +------------------------------------------------------------+
15 +--------+ | +----------------+ +-----------+ |
16 | DPDMA | --->| | --> | Video | Video +-------------+ |
17 | 4x vid | | | | | Rendering | -+--> | | | +------+
18 | 2x aud | | | Audio/Video | --> | Pipeline | | | DisplayPort |---> | PHY0 |
19 +--------+ | | Buffer Manager | +-----------+ | | Source | | +------+
20 | | and STC | +-----------+ | | Controller | | +------+
21 Live Video --->| | --> | Audio | Audio | |---> | PHY1 |
22 | | | | Mixer | --+-> | | | +------+
23 Live Audio --->| | --> | | || +-------------+ |
24 | +----------------+ +-----------+ || |
25 +---------------------------------------||-------------------+
41 (https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf)
45 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
49 const: xlnx,zynqmp-dpsub-1.7
53 reg-names:
55 - const: dp
56 - const: blend
57 - const: av_buf
58 - const: aud
69 - description: dp_apb_clk is the APB clock
70 - description: dp_aud_clk is the Audio clock
71 - description:
72 dp_vtc_pixel_clk_in is the non-live video clock (from Processing
74 - description:
77 clock-names:
79 - minItems: 2
81 - const: dp_apb_clk
82 - enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ]
83 - enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ]
84 - minItems: 3
86 - const: dp_apb_clk
87 - const: dp_aud_clk
88 - enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ]
89 - enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ]
91 power-domains:
99 - description: Video layer, plane 0 (RGB or luma)
100 - description: Video layer, plane 1 (U/V or U)
101 - description: Video layer, plane 2 (V)
102 - description: Graphics layer
103 dma-names:
105 - const: vid0
106 - const: vid1
107 - const: vid2
108 - const: gfx0
114 phy-names:
117 - const: dp-phy0
118 - const: dp-phy1
152 - port@0
153 - port@1
154 - port@2
155 - port@3
156 - port@4
157 - port@5
160 - compatible
161 - reg
162 - reg-names
163 - interrupts
164 - clocks
165 - clock-names
166 - power-domains
167 - resets
168 - dmas
169 - dma-names
170 - phys
171 - phy-names
172 - ports
177 - |
178 #include <dt-bindings/phy/phy.h>
179 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
182 compatible = "xlnx,zynqmp-dpsub-1.7";
187 reg-names = "dp", "blend", "av_buf", "aud";
189 interrupt-parent = <&gic>;
191 clock-names = "dp_apb_clk", "dp_aud_clk", "dp_live_video_in_clk";
194 power-domains = <&pd_dp>;
197 dma-names = "vid0", "vid1", "vid2", "gfx0";
206 phy-names = "dp-phy0", "dp-phy1";
209 #address-cells = <1>;
210 #size-cells = <0>;
230 remote-endpoint = <&dp_connector>;