Lines Matching +full:max +full:- +full:memory +full:- +full:bandwidth
4 See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic
8 --------
11 - compatible: "ti,dra7-dss"
12 - reg: address and length of the register spaces for 'dss'
13 - ti,hwmods: "dss_core"
14 - clocks: handle to fclk
15 - clock-names: "fck"
16 - syscon: phandle to control module core syscon node
23 - reg: address and length of the register spaces for 'pll1_clkctrl',
25 - clocks: handle to video1 pll clock and video2 pll clock
26 - clock-names: "video1_clk" and "video2_clk"
29 - DISPC
32 - DSS Submodules: HDMI
33 - Video port for DPI output
36 - data-lines: number of lines used
40 -----
43 - compatible: "ti,dra7-dispc"
44 - reg: address and length of the register space
45 - ti,hwmods: "dss_dispc"
46 - interrupts: the DISPC interrupt
47 - clocks: handle to fclk
48 - clock-names: "fck"
51 - max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit
56 ----
59 - compatible: "ti,dra7-hdmi"
60 - reg: addresses and lengths of the register spaces for 'wp', 'pll', 'phy',
62 - reg-names: "wp", "pll", "phy", "core"
63 - interrupts: the HDMI interrupt line
64 - ti,hwmods: "dss_hdmi"
65 - vdda-supply: vdda power supply
66 - clocks: handles to fclk and pll clock
67 - clock-names: "fck", "sys_clk"
70 - Video port for HDMI output
73 - lanes: list of 8 pin numbers for the HDMI lanes: CLK+, CLK-, D0+, D0-,
74 D1+, D1-, D2+, D2-. (default: 0,1,2,3,4,5,6,7)