Lines Matching +full:clock +full:- +full:falling +full:- +full:edge
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/panel/panel-timing.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Sam Ravnborg <sam@ravnborg.org>
20 +-------+----------+-------------------------------------+----------+
24 +-------+----------+-------------------------------------+----------+
28 +-------+----------#######################################----------+
33 |<----->|<-------->#<-------+--------------------------->#<-------->|
38 +-------+----------#######################################----------+
42 +-------+----------+-------------------------------------+----------+
45 The following is the panel timings shown with time on the x-axis.
50 <-----------------------><----------------><-------------><-------------->
61 clock-frequency:
62 description: Panel clock in Hz
72 hfront-porch:
74 $ref: /schemas/types.yaml#/definitions/uint32-array
76 - maxItems: 1
79 - minItems: 3
84 hback-porch:
86 $ref: /schemas/types.yaml#/definitions/uint32-array
88 - maxItems: 1
91 - minItems: 3
96 hsync-len:
98 $ref: /schemas/types.yaml#/definitions/uint32-array
100 - maxItems: 1
103 - minItems: 3
108 vfront-porch:
110 $ref: /schemas/types.yaml#/definitions/uint32-array
112 - maxItems: 1
115 - minItems: 3
120 vback-porch:
122 $ref: /schemas/types.yaml#/definitions/uint32-array
124 - maxItems: 1
127 - minItems: 3
132 vsync-len:
134 $ref: /schemas/types.yaml#/definitions/uint32-array
136 - maxItems: 1
139 - minItems: 3
144 hsync-active:
152 vsync-active:
160 de-active:
168 pixelclk-active:
170 Data driving on rising or falling edge.
171 Use 0 to drive pixel data on falling edge and
172 sample data on rising edge.
173 Use 1 to drive pixel data on rising edge and
174 sample data on falling edge
178 syncclk-active:
180 Drive sync on rising or sample sync on falling edge.
181 If not specified then the setup is as specified by pixelclk-active.
182 Use 0 to drive sync on falling edge and
183 sample sync on rising edge of pixel clock.
184 Use 1 to drive sync on rising edge and
185 sample sync on falling edge of pixel clock
199 description: Enable double clock mode
202 - clock-frequency
203 - hactive
204 - vactive
205 - hfront-porch
206 - hback-porch
207 - hsync-len
208 - vfront-porch
209 - vback-porch
210 - vsync-len