Lines Matching +full:dsi +full:- +full:phy
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8650-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Neil Armstrong <neil.armstrong@linaro.org>
13 SM8650 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
14 DPU display controller, DSI and DP interfaces etc.
16 $ref: /schemas/display/msm/mdss-common.yaml#
20 const: qcom,sm8650-mdss
24 - description: Display AHB
25 - description: Display hf AXI
26 - description: Display core
34 interconnect-names:
38 "^display-controller@[0-9a-f]+$":
43 const: qcom,sm8650-dpu
45 "^displayport-controller@[0-9a-f]+$":
50 const: qcom,sm8650-dp
52 "^dsi@[0-9a-f]+$":
58 - const: qcom,sm8650-dsi-ctrl
59 - const: qcom,mdss-dsi-ctrl
61 "^phy@[0-9a-f]+$":
66 const: qcom,sm8650-dsi-phy-4nm
69 - compatible
74 - |
75 #include <dt-bindings/clock/qcom,rpmh.h>
76 #include <dt-bindings/interrupt-controller/arm-gic.h>
77 #include <dt-bindings/power/qcom,rpmhpd.h>
79 display-subsystem@ae00000 {
80 compatible = "qcom,sm8650-mdss";
82 reg-names = "mdss";
86 power-domains = <&dispcc_gdsc>;
91 clock-names = "bus", "nrt_bus", "core";
94 interrupt-controller;
95 #interrupt-cells = <1>;
99 #address-cells = <1>;
100 #size-cells = <1>;
103 display-controller@ae01000 {
104 compatible = "qcom,sm8650-dpu";
107 reg-names = "mdp", "vbif";
114 clock-names = "nrt_bus",
120 assigned-clocks = <&dispcc_mdp_vsync_clk>;
121 assigned-clock-rates = <19200000>;
123 operating-points-v2 = <&mdp_opp_table>;
124 power-domains = <&rpmhpd RPMHPD_MMCX>;
126 interrupt-parent = <&mdss>;
130 #address-cells = <1>;
131 #size-cells = <0>;
136 remote-endpoint = <&dsi0_in>;
143 remote-endpoint = <&dsi1_in>;
148 mdp_opp_table: opp-table {
149 compatible = "operating-points-v2";
151 opp-200000000 {
152 opp-hz = /bits/ 64 <200000000>;
153 required-opps = <&rpmhpd_opp_low_svs>;
156 opp-325000000 {
157 opp-hz = /bits/ 64 <325000000>;
158 required-opps = <&rpmhpd_opp_svs>;
161 opp-375000000 {
162 opp-hz = /bits/ 64 <375000000>;
163 required-opps = <&rpmhpd_opp_svs_l1>;
166 opp-514000000 {
167 opp-hz = /bits/ 64 <514000000>;
168 required-opps = <&rpmhpd_opp_nom>;
173 dsi@ae94000 {
174 compatible = "qcom,sm8650-dsi-ctrl", "qcom,mdss-dsi-ctrl";
176 reg-names = "dsi_ctrl";
178 interrupt-parent = <&mdss>;
187 clock-names = "byte",
194 assigned-clocks = <&dispcc_byte_clk>,
196 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
198 operating-points-v2 = <&dsi_opp_table>;
199 power-domains = <&rpmhpd RPMHPD_MMCX>;
202 phy-names = "dsi";
204 #address-cells = <1>;
205 #size-cells = <0>;
208 #address-cells = <1>;
209 #size-cells = <0>;
214 remote-endpoint = <&dpu_intf1_out>;
225 dsi_opp_table: opp-table {
226 compatible = "operating-points-v2";
228 opp-187500000 {
229 opp-hz = /bits/ 64 <187500000>;
230 required-opps = <&rpmhpd_opp_low_svs>;
233 opp-300000000 {
234 opp-hz = /bits/ 64 <300000000>;
235 required-opps = <&rpmhpd_opp_svs>;
238 opp-358000000 {
239 opp-hz = /bits/ 64 <358000000>;
240 required-opps = <&rpmhpd_opp_svs_l1>;
245 dsi0_phy: phy@ae94400 {
246 compatible = "qcom,sm8650-dsi-phy-4nm";
250 reg-names = "dsi_phy",
254 #clock-cells = <1>;
255 #phy-cells = <0>;
259 clock-names = "iface", "ref";
262 dsi@ae96000 {
263 compatible = "qcom,sm8650-dsi-ctrl", "qcom,mdss-dsi-ctrl";
265 reg-names = "dsi_ctrl";
267 interrupt-parent = <&mdss>;
276 clock-names = "byte",
283 assigned-clocks = <&dispcc_byte_clk>,
285 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
287 operating-points-v2 = <&dsi_opp_table>;
288 power-domains = <&rpmhpd RPMHPD_MMCX>;
291 phy-names = "dsi";
293 #address-cells = <1>;
294 #size-cells = <0>;
297 #address-cells = <1>;
298 #size-cells = <0>;
303 remote-endpoint = <&dpu_intf2_out>;
315 dsi1_phy: phy@ae96400 {
316 compatible = "qcom,sm8650-dsi-phy-4nm";
320 reg-names = "dsi_phy",
324 #clock-cells = <1>;
325 #phy-cells = <0>;
329 clock-names = "iface", "ref";