Lines Matching +full:0 +full:x0ae97200

38   "^display-controller@[0-9a-f]+$":
45   "^displayport-controller@[0-9a-f]+$":
52   "^dsi@[0-9a-f]+$":
61   "^phy@[0-9a-f]+$":
81         reg = <0x0ae00000 0x1000>;
97         iommus = <&apps_smmu 0x1c00 0x2>;
105             reg = <0x0ae01000 0x8f000>,
106                   <0x0aeb0000 0x2008>;
127             interrupts = <0>;
131                 #size-cells = <0>;
133                 port@0 {
134                     reg = <0>;
175             reg = <0x0ae94000 0x400>;
196             assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
205             #size-cells = <0>;
209                 #size-cells = <0>;
211                 port@0 {
212                     reg = <0>;
247             reg = <0x0ae95000 0x200>,
248                   <0x0ae95200 0x280>,
249                   <0x0ae95500 0x400>;
255             #phy-cells = <0>;
264             reg = <0x0ae96000 0x400>;
285             assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
294             #size-cells = <0>;
298                 #size-cells = <0>;
300                 port@0 {
301                     reg = <0>;
317             reg = <0x0ae97000 0x200>,
318                   <0x0ae97200 0x280>,
319                   <0x0ae97500 0x400>;
325             #phy-cells = <0>;