Lines Matching +full:sm8550 +full:- +full:dpu
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8550-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SM8550 Display MDSS
10 - Neil Armstrong <neil.armstrong@linaro.org>
13 SM8550 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
14 DPU display controller, DSI and DP interfaces etc.
16 $ref: /schemas/display/msm/mdss-common.yaml#
20 const: qcom,sm8550-mdss
24 - description: Display MDSS AHB
25 - description: Display AHB
26 - description: Display hf AXI
27 - description: Display core
35 interconnect-names:
39 "^display-controller@[0-9a-f]+$":
45 const: qcom,sm8550-dpu
47 "^displayport-controller@[0-9a-f]+$":
54 - const: qcom,sm8550-dp
55 - const: qcom,sm8350-dp
57 "^dsi@[0-9a-f]+$":
64 - const: qcom,sm8550-dsi-ctrl
65 - const: qcom,mdss-dsi-ctrl
67 "^phy@[0-9a-f]+$":
73 const: qcom,sm8550-dsi-phy-4nm
76 - compatible
81 - |
82 #include <dt-bindings/clock/qcom,sm8550-dispcc.h>
83 #include <dt-bindings/clock/qcom,sm8550-gcc.h>
84 #include <dt-bindings/clock/qcom,rpmh.h>
85 #include <dt-bindings/interrupt-controller/arm-gic.h>
86 #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
87 #include <dt-bindings/power/qcom,rpmhpd.h>
89 display-subsystem@ae00000 {
90 compatible = "qcom,sm8550-mdss";
92 reg-names = "mdss";
96 interconnect-names = "mdp0-mem", "mdp1-mem";
100 power-domains = <&dispcc MDSS_GDSC>;
106 clock-names = "iface", "bus", "nrt_bus", "core";
109 interrupt-controller;
110 #interrupt-cells = <1>;
114 #address-cells = <1>;
115 #size-cells = <1>;
118 display-controller@ae01000 {
119 compatible = "qcom,sm8550-dpu";
122 reg-names = "mdp", "vbif";
130 clock-names = "bus",
137 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
138 assigned-clock-rates = <19200000>;
140 operating-points-v2 = <&mdp_opp_table>;
141 power-domains = <&rpmhpd RPMHPD_MMCX>;
143 interrupt-parent = <&mdss>;
147 #address-cells = <1>;
148 #size-cells = <0>;
153 remote-endpoint = <&dsi0_in>;
160 remote-endpoint = <&dsi1_in>;
165 mdp_opp_table: opp-table {
166 compatible = "operating-points-v2";
168 opp-200000000 {
169 opp-hz = /bits/ 64 <200000000>;
170 required-opps = <&rpmhpd_opp_low_svs>;
173 opp-325000000 {
174 opp-hz = /bits/ 64 <325000000>;
175 required-opps = <&rpmhpd_opp_svs>;
178 opp-375000000 {
179 opp-hz = /bits/ 64 <375000000>;
180 required-opps = <&rpmhpd_opp_svs_l1>;
183 opp-514000000 {
184 opp-hz = /bits/ 64 <514000000>;
185 required-opps = <&rpmhpd_opp_nom>;
191 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl";
193 reg-names = "dsi_ctrl";
195 interrupt-parent = <&mdss>;
204 clock-names = "byte",
211 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
213 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
215 operating-points-v2 = <&dsi_opp_table>;
216 power-domains = <&rpmhpd RPMHPD_MMCX>;
219 phy-names = "dsi";
221 #address-cells = <1>;
222 #size-cells = <0>;
225 #address-cells = <1>;
226 #size-cells = <0>;
231 remote-endpoint = <&dpu_intf1_out>;
242 dsi_opp_table: opp-table {
243 compatible = "operating-points-v2";
245 opp-187500000 {
246 opp-hz = /bits/ 64 <187500000>;
247 required-opps = <&rpmhpd_opp_low_svs>;
250 opp-300000000 {
251 opp-hz = /bits/ 64 <300000000>;
252 required-opps = <&rpmhpd_opp_svs>;
255 opp-358000000 {
256 opp-hz = /bits/ 64 <358000000>;
257 required-opps = <&rpmhpd_opp_svs_l1>;
263 compatible = "qcom,sm8550-dsi-phy-4nm";
267 reg-names = "dsi_phy",
271 #clock-cells = <1>;
272 #phy-cells = <0>;
276 clock-names = "iface", "ref";
280 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl";
282 reg-names = "dsi_ctrl";
284 interrupt-parent = <&mdss>;
293 clock-names = "byte",
300 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
302 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
304 operating-points-v2 = <&dsi_opp_table>;
305 power-domains = <&rpmhpd RPMHPD_MMCX>;
308 phy-names = "dsi";
310 #address-cells = <1>;
311 #size-cells = <0>;
314 #address-cells = <1>;
315 #size-cells = <0>;
320 remote-endpoint = <&dpu_intf2_out>;
333 compatible = "qcom,sm8550-dsi-phy-4nm";
337 reg-names = "dsi_phy",
341 #clock-cells = <1>;
342 #phy-cells = <0>;
346 clock-names = "iface", "ref";