Lines Matching +full:opp +full:- +full:358000000
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8550-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Neil Armstrong <neil.armstrong@linaro.org>
13 SM8550 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
16 $ref: /schemas/display/msm/mdss-common.yaml#
20 const: qcom,sm8550-mdss
24 - description: Display MDSS AHB
25 - description: Display AHB
26 - description: Display hf AXI
27 - description: Display core
34 - description: Interconnect path from mdp0 port to the data bus
35 - description: Interconnect path from CPU to the reg bus
37 interconnect-names:
39 - const: mdp0-mem
40 - const: cpu-cfg
43 "^display-controller@[0-9a-f]+$":
49 const: qcom,sm8550-dpu
51 "^displayport-controller@[0-9a-f]+$":
58 - const: qcom,sm8550-dp
59 - const: qcom,sm8350-dp
61 "^dsi@[0-9a-f]+$":
68 - const: qcom,sm8550-dsi-ctrl
69 - const: qcom,mdss-dsi-ctrl
71 "^phy@[0-9a-f]+$":
77 const: qcom,sm8550-dsi-phy-4nm
80 - compatible
85 - |
86 #include <dt-bindings/clock/qcom,sm8550-dispcc.h>
87 #include <dt-bindings/clock/qcom,sm8550-gcc.h>
88 #include <dt-bindings/clock/qcom,rpmh.h>
89 #include <dt-bindings/interrupt-controller/arm-gic.h>
90 #include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
91 #include <dt-bindings/power/qcom,rpmhpd.h>
93 display-subsystem@ae00000 {
94 compatible = "qcom,sm8550-mdss";
96 reg-names = "mdss";
100 interconnect-names = "mdp0-mem", "cpu-cfg";
104 power-domains = <&dispcc MDSS_GDSC>;
110 clock-names = "iface", "bus", "nrt_bus", "core";
113 interrupt-controller;
114 #interrupt-cells = <1>;
118 #address-cells = <1>;
119 #size-cells = <1>;
122 display-controller@ae01000 {
123 compatible = "qcom,sm8550-dpu";
126 reg-names = "mdp", "vbif";
134 clock-names = "bus",
141 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
142 assigned-clock-rates = <19200000>;
144 operating-points-v2 = <&mdp_opp_table>;
145 power-domains = <&rpmhpd RPMHPD_MMCX>;
147 interrupt-parent = <&mdss>;
151 #address-cells = <1>;
152 #size-cells = <0>;
157 remote-endpoint = <&dsi0_in>;
164 remote-endpoint = <&dsi1_in>;
169 mdp_opp_table: opp-table {
170 compatible = "operating-points-v2";
172 opp-200000000 {
173 opp-hz = /bits/ 64 <200000000>;
174 required-opps = <&rpmhpd_opp_low_svs>;
177 opp-325000000 {
178 opp-hz = /bits/ 64 <325000000>;
179 required-opps = <&rpmhpd_opp_svs>;
182 opp-375000000 {
183 opp-hz = /bits/ 64 <375000000>;
184 required-opps = <&rpmhpd_opp_svs_l1>;
187 opp-514000000 {
188 opp-hz = /bits/ 64 <514000000>;
189 required-opps = <&rpmhpd_opp_nom>;
195 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl";
197 reg-names = "dsi_ctrl";
199 interrupt-parent = <&mdss>;
208 clock-names = "byte",
215 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
217 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
219 operating-points-v2 = <&dsi_opp_table>;
220 power-domains = <&rpmhpd RPMHPD_MMCX>;
223 phy-names = "dsi";
225 #address-cells = <1>;
226 #size-cells = <0>;
229 #address-cells = <1>;
230 #size-cells = <0>;
235 remote-endpoint = <&dpu_intf1_out>;
246 dsi_opp_table: opp-table {
247 compatible = "operating-points-v2";
249 opp-187500000 {
250 opp-hz = /bits/ 64 <187500000>;
251 required-opps = <&rpmhpd_opp_low_svs>;
254 opp-300000000 {
255 opp-hz = /bits/ 64 <300000000>;
256 required-opps = <&rpmhpd_opp_svs>;
259 opp-358000000 {
260 opp-hz = /bits/ 64 <358000000>;
261 required-opps = <&rpmhpd_opp_svs_l1>;
267 compatible = "qcom,sm8550-dsi-phy-4nm";
271 reg-names = "dsi_phy",
275 #clock-cells = <1>;
276 #phy-cells = <0>;
280 clock-names = "iface", "ref";
284 compatible = "qcom,sm8550-dsi-ctrl", "qcom,mdss-dsi-ctrl";
286 reg-names = "dsi_ctrl";
288 interrupt-parent = <&mdss>;
297 clock-names = "byte",
304 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
306 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
308 operating-points-v2 = <&dsi_opp_table>;
309 power-domains = <&rpmhpd RPMHPD_MMCX>;
312 phy-names = "dsi";
314 #address-cells = <1>;
315 #size-cells = <0>;
318 #address-cells = <1>;
319 #size-cells = <0>;
324 remote-endpoint = <&dpu_intf2_out>;
337 compatible = "qcom,sm8550-dsi-phy-4nm";
341 reg-names = "dsi_phy",
345 #clock-cells = <1>;
346 #phy-cells = <0>;
350 clock-names = "iface", "ref";