Lines Matching +full:sm8350 +full:- +full:dsi +full:- +full:ctrl
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8350-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SM8350 Display MDSS
10 - Robert Foss <robert.foss@linaro.org>
13 MSM Mobile Display Subsystem(MDSS) that encapsulates sub-blocks like
14 DPU display controller, DSI and DP interfaces etc.
16 $ref: /schemas/display/msm/mdss-common.yaml#
21 - const: qcom,sm8350-mdss
25 - description: Display AHB clock from gcc
26 - description: Display hf axi clock
27 - description: Display sf axi clock
28 - description: Display core clock
30 clock-names:
32 - const: iface
33 - const: bus
34 - const: nrt_bus
35 - const: core
42 - description: Interconnect path from the MDP0 port to the data bus
43 - description: Interconnect path from the MDP1 port to the data bus
44 - description: Interconnect path from the CPU to the reg bus
46 interconnect-names:
48 - const: mdp0-mem
49 - const: mdp1-mem
50 - const: cpu-cfg
53 "^display-controller@[0-9a-f]+$":
59 const: qcom,sm8350-dpu
61 "^displayport-controller@[0-9a-f]+$":
67 const: qcom,sm8350-dp
69 "^dsi@[0-9a-f]+$":
76 - const: qcom,sm8350-dsi-ctrl
77 - const: qcom,mdss-dsi-ctrl
79 "^phy@[0-9a-f]+$":
85 const: qcom,sm8350-dsi-phy-5nm
90 - |
91 #include <dt-bindings/clock/qcom,dispcc-sm8350.h>
92 #include <dt-bindings/clock/qcom,gcc-sm8350.h>
93 #include <dt-bindings/clock/qcom,rpmh.h>
94 #include <dt-bindings/interrupt-controller/arm-gic.h>
95 #include <dt-bindings/interconnect/qcom,icc.h>
96 #include <dt-bindings/interconnect/qcom,sm8350.h>
97 #include <dt-bindings/power/qcom,rpmhpd.h>
99 display-subsystem@ae00000 {
100 compatible = "qcom,sm8350-mdss";
102 reg-names = "mdss";
108 interconnect-names = "mdp0-mem", "mdp1-mem", "cpu-cfg";
110 power-domains = <&dispcc MDSS_GDSC>;
117 clock-names = "iface", "bus", "nrt_bus", "core";
122 interrupt-controller;
123 #interrupt-cells = <1>;
125 #address-cells = <1>;
126 #size-cells = <1>;
129 display-controller@ae01000 {
130 compatible = "qcom,sm8350-dpu";
133 reg-names = "mdp", "vbif";
141 clock-names = "bus",
148 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
149 assigned-clock-rates = <19200000>;
151 operating-points-v2 = <&mdp_opp_table>;
152 power-domains = <&rpmhpd RPMHPD_MMCX>;
154 interrupt-parent = <&mdss>;
158 #address-cells = <1>;
159 #size-cells = <0>;
164 remote-endpoint = <&dsi0_in>;
169 mdp_opp_table: opp-table {
170 compatible = "operating-points-v2";
172 opp-200000000 {
173 opp-hz = /bits/ 64 <200000000>;
174 required-opps = <&rpmhpd_opp_low_svs>;
177 opp-300000000 {
178 opp-hz = /bits/ 64 <300000000>;
179 required-opps = <&rpmhpd_opp_svs>;
182 opp-345000000 {
183 opp-hz = /bits/ 64 <345000000>;
184 required-opps = <&rpmhpd_opp_svs_l1>;
187 opp-460000000 {
188 opp-hz = /bits/ 64 <460000000>;
189 required-opps = <&rpmhpd_opp_nom>;
194 dsi0: dsi@ae94000 {
195 compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
197 reg-names = "dsi_ctrl";
199 interrupt-parent = <&mdss>;
208 clock-names = "byte",
215 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
217 assigned-clock-parents = <&mdss_dsi0_phy 0>,
220 operating-points-v2 = <&dsi_opp_table>;
221 power-domains = <&rpmhpd RPMHPD_MMCX>;
226 #address-cells = <1>;
227 #size-cells = <0>;
232 remote-endpoint = <&dpu_intf1_out>;