Lines Matching +full:dispcc +full:- +full:sm8350
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8350-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SM8350 Display MDSS
10 - Robert Foss <robert.foss@linaro.org>
13 MSM Mobile Display Subsystem(MDSS) that encapsulates sub-blocks like
16 $ref: /schemas/display/msm/mdss-common.yaml#
21 - const: qcom,sm8350-mdss
25 - description: Display AHB clock from gcc
26 - description: Display hf axi clock
27 - description: Display sf axi clock
28 - description: Display core clock
30 clock-names:
32 - const: iface
33 - const: bus
34 - const: nrt_bus
35 - const: core
43 interconnect-names:
45 - const: mdp0-mem
46 - const: mdp1-mem
49 "^display-controller@[0-9a-f]+$":
55 const: qcom,sm8350-dpu
57 "^displayport-controller@[0-9a-f]+$":
63 const: qcom,sm8350-dp
65 "^dsi@[0-9a-f]+$":
72 - const: qcom,sm8350-dsi-ctrl
73 - const: qcom,mdss-dsi-ctrl
75 "^phy@[0-9a-f]+$":
81 const: qcom,sm8350-dsi-phy-5nm
86 - |
87 #include <dt-bindings/clock/qcom,dispcc-sm8350.h>
88 #include <dt-bindings/clock/qcom,gcc-sm8350.h>
89 #include <dt-bindings/clock/qcom,rpmh.h>
90 #include <dt-bindings/interrupt-controller/arm-gic.h>
91 #include <dt-bindings/interconnect/qcom,sm8350.h>
92 #include <dt-bindings/power/qcom,rpmhpd.h>
94 display-subsystem@ae00000 {
95 compatible = "qcom,sm8350-mdss";
97 reg-names = "mdss";
101 interconnect-names = "mdp0-mem", "mdp1-mem";
103 power-domains = <&dispcc MDSS_GDSC>;
104 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
106 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
109 <&dispcc DISP_CC_MDSS_MDP_CLK>;
110 clock-names = "iface", "bus", "nrt_bus", "core";
115 interrupt-controller;
116 #interrupt-cells = <1>;
118 #address-cells = <1>;
119 #size-cells = <1>;
122 display-controller@ae01000 {
123 compatible = "qcom,sm8350-dpu";
126 reg-names = "mdp", "vbif";
130 <&dispcc DISP_CC_MDSS_AHB_CLK>,
131 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
132 <&dispcc DISP_CC_MDSS_MDP_CLK>,
133 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
134 clock-names = "bus",
141 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
142 assigned-clock-rates = <19200000>;
144 operating-points-v2 = <&mdp_opp_table>;
145 power-domains = <&rpmhpd RPMHPD_MMCX>;
147 interrupt-parent = <&mdss>;
151 #address-cells = <1>;
152 #size-cells = <0>;
157 remote-endpoint = <&dsi0_in>;
162 mdp_opp_table: opp-table {
163 compatible = "operating-points-v2";
165 opp-200000000 {
166 opp-hz = /bits/ 64 <200000000>;
167 required-opps = <&rpmhpd_opp_low_svs>;
170 opp-300000000 {
171 opp-hz = /bits/ 64 <300000000>;
172 required-opps = <&rpmhpd_opp_svs>;
175 opp-345000000 {
176 opp-hz = /bits/ 64 <345000000>;
177 required-opps = <&rpmhpd_opp_svs_l1>;
180 opp-460000000 {
181 opp-hz = /bits/ 64 <460000000>;
182 required-opps = <&rpmhpd_opp_nom>;
188 compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
190 reg-names = "dsi_ctrl";
192 interrupt-parent = <&mdss>;
195 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
196 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
197 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
198 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
199 <&dispcc DISP_CC_MDSS_AHB_CLK>,
201 clock-names = "byte",
208 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
209 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
210 assigned-clock-parents = <&mdss_dsi0_phy 0>,
213 operating-points-v2 = <&dsi_opp_table>;
214 power-domains = <&rpmhpd RPMHPD_MMCX>;
219 #address-cells = <1>;
220 #size-cells = <0>;
225 remote-endpoint = <&dpu_intf1_out>;