Lines Matching +full:sm7150 +full:- +full:dp
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm7150-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SM7150 Display MDSS
10 - Danila Tikhonov <danila@jiaxyga.com>
13 SM7150 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like
14 DPU display controller, DSI and DP interfaces etc.
16 $ref: /schemas/display/msm/mdss-common.yaml#
20 const: qcom,sm7150-mdss
24 - description: Display ahb clock from gcc
25 - description: Display hf axi clock
26 - description: Display sf axi clock
27 - description: Display core clock
29 clock-names:
31 - const: iface
32 - const: bus
33 - const: nrt_bus
34 - const: core
41 - description: Interconnect path from mdp0 port to the data bus
42 - description: Interconnect path from mdp1 port to the data bus
43 - description: Interconnect path from CPU to the reg bus
45 interconnect-names:
47 - const: mdp0-mem
48 - const: mdp1-mem
49 - const: cpu-cfg
52 "^display-controller@[0-9a-f]+$":
57 const: qcom,sm7150-dpu
59 "^displayport-controller@[0-9a-f]+$":
64 const: qcom,sm7150-dp
66 "^dsi@[0-9a-f]+$":
72 - const: qcom,sm7150-dsi-ctrl
73 - const: qcom,mdss-dsi-ctrl
75 "^phy@[0-9a-f]+$":
80 const: qcom,dsi-phy-10nm
83 - compatible
88 - |
89 #include <dt-bindings/clock/qcom,rpmh.h>
90 #include <dt-bindings/interconnect/qcom,icc.h>
91 #include <dt-bindings/interconnect/qcom,sm7150-rpmh.h>
92 #include <dt-bindings/interrupt-controller/arm-gic.h>
93 #include <dt-bindings/power/qcom,rpmhpd.h>
95 display-subsystem@ae00000 {
96 compatible = "qcom,sm7150-mdss";
98 reg-names = "mdss";
100 power-domains = <&dispcc_mdss_gdsc>;
106 clock-names = "iface",
112 interrupt-controller;
113 #interrupt-cells = <1>;
121 interconnect-names = "mdp0-mem",
122 "mdp1-mem",
123 "cpu-cfg";
127 #address-cells = <1>;
128 #size-cells = <1>;
131 display-controller@ae01000 {
132 compatible = "qcom,sm7150-dpu";
135 reg-names = "mdp", "vbif";
143 clock-names = "bus",
150 assigned-clocks = <&dispcc_mdss_vsync_clk>;
151 assigned-clock-rates = <19200000>;
153 operating-points-v2 = <&mdp_opp_table>;
154 power-domains = <&rpmhpd RPMHPD_CX>;
156 interrupt-parent = <&mdss>;
160 #address-cells = <1>;
161 #size-cells = <0>;
166 remote-endpoint = <&mdss_dsi0_in>;
173 remote-endpoint = <&mdss_dsi1_in>;
180 remote-endpoint = <&dp_in>;
185 mdp_opp_table: opp-table {
186 compatible = "operating-points-v2";
188 opp-19200000 {
189 opp-hz = /bits/ 64 <19200000>;
190 required-opps = <&rpmhpd_opp_min_svs>;
193 opp-200000000 {
194 opp-hz = /bits/ 64 <200000000>;
195 required-opps = <&rpmhpd_opp_low_svs>;
198 opp-300000000 {
199 opp-hz = /bits/ 64 <300000000>;
200 required-opps = <&rpmhpd_opp_svs>;
203 opp-344000000 {
204 opp-hz = /bits/ 64 <344000000>;
205 required-opps = <&rpmhpd_opp_svs_l1>;
208 opp-430000000 {
209 opp-hz = /bits/ 64 <430000000>;
210 required-opps = <&rpmhpd_opp_nom>;
216 compatible = "qcom,sm7150-dsi-ctrl",
217 "qcom,mdss-dsi-ctrl";
219 reg-names = "dsi_ctrl";
221 interrupt-parent = <&mdss>;
230 clock-names = "byte",
237 assigned-clocks = <&dispcc_mdss_byte0_clk_src>,
239 assigned-clock-parents = <&mdss_dsi0_phy 0>,
242 operating-points-v2 = <&dsi_opp_table>;
243 power-domains = <&rpmhpd RPMHPD_CX>;
246 phy-names = "dsi";
248 #address-cells = <1>;
249 #size-cells = <0>;
252 #address-cells = <1>;
253 #size-cells = <0>;
258 remote-endpoint = <&dpu_intf1_out>;
269 dsi_opp_table: opp-table {
270 compatible = "operating-points-v2";
272 opp-180000000 {
273 opp-hz = /bits/ 64 <180000000>;
274 required-opps = <&rpmhpd_opp_low_svs>;
277 opp-275000000 {
278 opp-hz = /bits/ 64 <275000000>;
279 required-opps = <&rpmhpd_opp_svs>;
282 opp-358000000 {
283 opp-hz = /bits/ 64 <358000000>;
284 required-opps = <&rpmhpd_opp_svs_l1>;
290 compatible = "qcom,dsi-phy-10nm";
294 reg-names = "dsi_phy",
298 #clock-cells = <1>;
299 #phy-cells = <0>;
303 clock-names = "iface", "ref";
304 vdds-supply = <&vdda_mipi_dsi0_pll>;
308 compatible = "qcom,sm7150-dsi-ctrl",
309 "qcom,mdss-dsi-ctrl";
311 reg-names = "dsi_ctrl";
313 interrupt-parent = <&mdss>;
322 clock-names = "byte",
329 assigned-clocks = <&dispcc_mdss_byte1_clk_src>,
331 assigned-clock-parents = <&mdss_dsi1_phy 0>,
334 operating-points-v2 = <&dsi_opp_table>;
335 power-domains = <&rpmhpd RPMHPD_CX>;
338 phy-names = "dsi";
340 #address-cells = <1>;
341 #size-cells = <0>;
344 #address-cells = <1>;
345 #size-cells = <0>;
350 remote-endpoint = <&dpu_intf2_out>;
363 compatible = "qcom,dsi-phy-10nm";
367 reg-names = "dsi_phy",
371 #clock-cells = <1>;
372 #phy-cells = <0>;
376 clock-names = "iface", "ref";
377 vdds-supply = <&vdda_mipi_dsi1_pll>;
380 displayport-controller@ae90000 {
381 compatible = "qcom,sm7150-dp";
388 interrupt-parent = <&mdss>;
396 clock-names = "core_iface",
402 assigned-clocks = <&dispcc_mdss_dp_link_clk_src>,
404 assigned-clock-parents = <&dp_phy 0>,
407 operating-points-v2 = <&dp_opp_table>;
408 power-domains = <&rpmhpd RPMHPD_CX>;
411 phy-names = "dp";
413 #sound-dai-cells = <0>;
416 #address-cells = <1>;
417 #size-cells = <0>;
422 remote-endpoint = <&dpu_intf0_out>;
433 dp_opp_table: opp-table {
434 compatible = "operating-points-v2";
436 opp-160000000 {
437 opp-hz = /bits/ 64 <160000000>;
438 required-opps = <&rpmhpd_opp_low_svs>;
441 opp-270000000 {
442 opp-hz = /bits/ 64 <270000000>;
443 required-opps = <&rpmhpd_opp_svs>;
446 opp-540000000 {
447 opp-hz = /bits/ 64 <540000000>;
448 required-opps = <&rpmhpd_opp_svs_l1>;
451 opp-810000000 {
452 opp-hz = /bits/ 64 <810000000>;
453 required-opps = <&rpmhpd_opp_nom>;