Lines Matching +full:0 +full:xae90200

52   "^display-controller@[0-9a-f]+$":
59   "^displayport-controller@[0-9a-f]+$":
66   "^dsi@[0-9a-f]+$":
75   "^phy@[0-9a-f]+$":
97         reg = <0x0ae00000 0x1000>;
125         iommus = <&apps_smmu 0x800 0x440>;
133             reg = <0x0ae01000 0x8f000>,
134                   <0x0aeb0000 0x2008>;
157             interrupts = <0>;
161                 #size-cells = <0>;
163                 port@0 {
164                     reg = <0>;
218             reg = <0x0ae94000 0x400>;
239             assigned-clock-parents = <&mdss_dsi0_phy 0>,
249             #size-cells = <0>;
253                 #size-cells = <0>;
255                 port@0 {
256                     reg = <0>;
291             reg = <0x0ae94400 0x200>,
292                   <0x0ae94600 0x280>,
293                   <0x0ae94a00 0x1e0>;
299             #phy-cells = <0>;
310             reg = <0x0ae96000 0x400>;
331             assigned-clock-parents = <&mdss_dsi1_phy 0>,
341             #size-cells = <0>;
345                 #size-cells = <0>;
347                 port@0 {
348                     reg = <0>;
364             reg = <0x0ae96400 0x200>,
365                   <0x0ae96600 0x280>,
366                   <0x0ae96a00 0x1e0>;
372             #phy-cells = <0>;
382             reg = <0xae90000 0x200>,
383                   <0xae90200 0x200>,
384                   <0xae90400 0xc00>,
385                   <0xae91000 0x400>,
386                   <0xae91400 0x400>;
404             assigned-clock-parents = <&dp_phy 0>,
413             #sound-dai-cells = <0>;
417                 #size-cells = <0>;
419                 port@0 {
420                     reg = <0>;