Lines Matching +full:dsi +full:- +full:controller
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm6375-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Konrad Dybcio <konradybcio@kernel.org>
13 SM6375 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks
14 like DPU display controller, DSI and DP interfaces etc.
16 $ref: /schemas/display/msm/mdss-common.yaml#
20 const: qcom,sm6375-mdss
24 - description: Display AHB clock from gcc
25 - description: Display AHB clock
26 - description: Display core clock
28 clock-names:
30 - const: iface
31 - const: ahb
32 - const: core
39 - description: Interconnect path from mdp0 port to the data bus
40 - description: Interconnect path from CPU to the reg bus
42 interconnect-names:
44 - const: mdp0-mem
45 - const: cpu-cfg
48 "^display-controller@[0-9a-f]+$":
54 const: qcom,sm6375-dpu
56 "^dsi@[0-9a-f]+$":
63 - const: qcom,sm6375-dsi-ctrl
64 - const: qcom,mdss-dsi-ctrl
66 "^phy@[0-9a-f]+$":
72 const: qcom,sm6375-dsi-phy-7nm
77 - |
78 #include <dt-bindings/clock/qcom,rpmcc.h>
79 #include <dt-bindings/clock/qcom,sm6375-gcc.h>
80 #include <dt-bindings/clock/qcom,sm6375-dispcc.h>
81 #include <dt-bindings/interrupt-controller/arm-gic.h>
82 #include <dt-bindings/power/qcom-rpmpd.h>
84 display-subsystem@5e00000 {
85 compatible = "qcom,sm6375-mdss";
87 reg-names = "mdss";
89 power-domains = <&dispcc MDSS_GDSC>;
94 clock-names = "iface", "ahb", "core";
97 interrupt-controller;
98 #interrupt-cells = <1>;
101 #address-cells = <1>;
102 #size-cells = <1>;
105 display-controller@5e01000 {
106 compatible = "qcom,sm6375-dpu";
109 reg-names = "mdp", "vbif";
118 clock-names = "bus",
126 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
127 assigned-clock-rates = <19200000>;
129 operating-points-v2 = <&mdp_opp_table>;
130 power-domains = <&rpmpd SM6375_VDDCX>;
132 interrupt-parent = <&mdss>;
136 #address-cells = <1>;
137 #size-cells = <0>;
142 remote-endpoint = <&dsi0_in>;
148 dsi@5e94000 {
149 compatible = "qcom,sm6375-dsi-ctrl", "qcom,mdss-dsi-ctrl";
151 reg-names = "dsi_ctrl";
153 interrupt-parent = <&mdss>;
162 clock-names = "byte",
169 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
171 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
173 operating-points-v2 = <&dsi_opp_table>;
174 power-domains = <&rpmpd SM6375_VDDMX>;
177 phy-names = "dsi";
179 #address-cells = <1>;
180 #size-cells = <0>;
183 #address-cells = <1>;
184 #size-cells = <0>;
189 remote-endpoint = <&dpu_intf1_out>;
202 compatible = "qcom,sm6375-dsi-phy-7nm";
206 reg-names = "dsi_phy",
210 #clock-cells = <1>;
211 #phy-cells = <0>;
215 clock-names = "iface", "ref";