Lines Matching +full:dsi +full:- +full:controller
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm6350-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
13 SM6350 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks
14 like DPU display controller, DSI and DP interfaces etc.
16 $ref: /schemas/display/msm/mdss-common.yaml#
20 const: qcom,sm6350-mdss
24 - description: Display AHB clock from gcc
25 - description: Display AXI clock from gcc
26 - description: Display core clock
28 clock-names:
30 - const: iface
31 - const: bus
32 - const: core
39 - description: Interconnect path from mdp0 port to the data bus
40 - description: Interconnect path from CPU to the reg bus
42 interconnect-names:
44 - const: mdp0-mem
45 - const: cpu-cfg
48 "^display-controller@[0-9a-f]+$":
54 const: qcom,sm6350-dpu
56 "^displayport-controller@[0-9a-f]+$":
63 const: qcom,sm6350-dp
65 "^dsi@[0-9a-f]+$":
72 - const: qcom,sm6350-dsi-ctrl
73 - const: qcom,mdss-dsi-ctrl
75 "^phy@[0-9a-f]+$":
81 const: qcom,dsi-phy-10nm
86 - |
87 #include <dt-bindings/clock/qcom,dispcc-sm6350.h>
88 #include <dt-bindings/clock/qcom,gcc-sm6350.h>
89 #include <dt-bindings/clock/qcom,rpmh.h>
90 #include <dt-bindings/interrupt-controller/arm-gic.h>
91 #include <dt-bindings/power/qcom-rpmpd.h>
93 display-subsystem@ae00000 {
94 compatible = "qcom,sm6350-mdss";
96 reg-names = "mdss";
98 power-domains = <&dispcc MDSS_GDSC>;
103 clock-names = "iface", "bus", "core";
106 interrupt-controller;
107 #interrupt-cells = <1>;
110 #address-cells = <1>;
111 #size-cells = <1>;
114 display-controller@ae01000 {
115 compatible = "qcom,sm6350-dpu";
118 reg-names = "mdp", "vbif";
126 clock-names = "bus", "iface", "rot", "lut", "core",
129 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
133 assigned-clock-rates = <300000000>,
138 interrupt-parent = <&mdss>;
140 operating-points-v2 = <&mdp_opp_table>;
141 power-domains = <&rpmhpd SM6350_CX>;
144 #address-cells = <1>;
145 #size-cells = <0>;
150 remote-endpoint = <&dsi0_in>;
156 dsi@ae94000 {
157 compatible = "qcom,sm6350-dsi-ctrl", "qcom,mdss-dsi-ctrl";
159 reg-names = "dsi_ctrl";
161 interrupt-parent = <&mdss>;
170 clock-names = "byte",
177 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
179 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
181 operating-points-v2 = <&dsi_opp_table>;
182 power-domains = <&rpmhpd SM6350_MX>;
185 phy-names = "dsi";
187 #address-cells = <1>;
188 #size-cells = <0>;
191 #address-cells = <1>;
192 #size-cells = <0>;
197 remote-endpoint = <&dpu_intf1_out>;
210 compatible = "qcom,dsi-phy-10nm";
214 reg-names = "dsi_phy",
218 #clock-cells = <1>;
219 #phy-cells = <0>;
222 clock-names = "iface", "ref";