Lines Matching +full:dsi +full:- +full:controller
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sdm845-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
17 $ref: /schemas/display/msm/mdss-common.yaml#
21 const: qcom,sdm845-mdss
25 - description: Display AHB clock from gcc
26 - description: Display core clock
28 clock-names:
30 - const: iface
31 - const: core
39 interconnect-names:
43 "^display-controller@[0-9a-f]+$":
49 const: qcom,sdm845-dpu
51 "^displayport-controller@[0-9a-f]+$":
57 const: qcom,sdm845-dp
59 "^dsi@[0-9a-f]+$":
66 - const: qcom,sdm845-dsi-ctrl
67 - const: qcom,mdss-dsi-ctrl
69 "^phy@[0-9a-f]+$":
75 const: qcom,dsi-phy-10nm
78 - compatible
83 - |
84 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
85 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
86 #include <dt-bindings/clock/qcom,rpmh.h>
87 #include <dt-bindings/interrupt-controller/arm-gic.h>
88 #include <dt-bindings/power/qcom-rpmpd.h>
90 display-subsystem@ae00000 {
91 #address-cells = <1>;
92 #size-cells = <1>;
93 compatible = "qcom,sdm845-mdss";
95 reg-names = "mdss";
96 power-domains = <&dispcc MDSS_GDSC>;
100 clock-names = "iface", "core";
103 interrupt-controller;
104 #interrupt-cells = <1>;
110 display-controller@ae01000 {
111 compatible = "qcom,sdm845-dpu";
114 reg-names = "mdp", "vbif";
121 clock-names = "gcc-bus", "iface", "bus", "core", "vsync";
123 interrupt-parent = <&mdss>;
125 power-domains = <&rpmhpd SDM845_CX>;
126 operating-points-v2 = <&mdp_opp_table>;
129 #address-cells = <1>;
130 #size-cells = <0>;
135 remote-endpoint = <&dsi0_in>;
142 remote-endpoint = <&dsi1_in>;
148 dsi@ae94000 {
149 compatible = "qcom,sdm845-dsi-ctrl", "qcom,mdss-dsi-ctrl";
151 reg-names = "dsi_ctrl";
153 interrupt-parent = <&mdss>;
162 clock-names = "byte",
168 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
170 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
172 operating-points-v2 = <&dsi_opp_table>;
173 power-domains = <&rpmhpd SDM845_CX>;
176 phy-names = "dsi";
178 #address-cells = <1>;
179 #size-cells = <0>;
182 #address-cells = <1>;
183 #size-cells = <0>;
188 remote-endpoint = <&dpu_intf1_out>;
201 compatible = "qcom,dsi-phy-10nm";
205 reg-names = "dsi_phy",
209 #clock-cells = <1>;
210 #phy-cells = <0>;
214 clock-names = "iface", "ref";
215 vdds-supply = <&vreg_dsi_phy>;
218 dsi@ae96000 {
219 compatible = "qcom,sdm845-dsi-ctrl", "qcom,mdss-dsi-ctrl";
221 reg-names = "dsi_ctrl";
223 interrupt-parent = <&mdss>;
232 clock-names = "byte",
238 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
240 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
242 operating-points-v2 = <&dsi_opp_table>;
243 power-domains = <&rpmhpd SDM845_CX>;
246 phy-names = "dsi";
248 #address-cells = <1>;
249 #size-cells = <0>;
252 #address-cells = <1>;
253 #size-cells = <0>;
258 remote-endpoint = <&dpu_intf2_out>;
271 compatible = "qcom,dsi-phy-10nm";
275 reg-names = "dsi_phy",
279 #clock-cells = <1>;
280 #phy-cells = <0>;
284 clock-names = "iface", "ref";
285 vdds-supply = <&vreg_dsi_phy>;