Lines Matching +full:0 +full:x10e
43 "^display-controller@[0-9a-f]+$":
51 "^displayport-controller@[0-9a-f]+$":
59 "^dsi@[0-9a-f]+$":
69 "^phy@[0-9a-f]+$":
94 reg = <0x0ae00000 0x1000>;
106 iommus = <&apps_smmu 0x880 0x8>,
107 <&apps_smmu 0xc80 0x8>;
112 reg = <0x0ae01000 0x8f000>,
113 <0x0aeb0000 0x2008>;
124 interrupts = <0>;
130 #size-cells = <0>;
132 port@0 {
133 reg = <0>;
150 reg = <0x0ae94000 0x400>;
170 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
179 #size-cells = <0>;
183 #size-cells = <0>;
185 port@0 {
186 reg = <0>;
202 reg = <0x0ae94400 0x200>,
203 <0x0ae94600 0x280>,
204 <0x0ae94a00 0x1e0>;
210 #phy-cells = <0>;
220 reg = <0x0ae96000 0x400>;
240 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
249 #size-cells = <0>;
253 #size-cells = <0>;
255 port@0 {
256 reg = <0>;
272 reg = <0x0ae96400 0x200>,
273 <0x0ae96600 0x280>,
274 <0x0ae96a00 0x10e>;
280 #phy-cells = <0>;