Lines Matching +full:dispcc +full:- +full:sdm845

1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sdm845-dpu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display DPU on SDM845
10   - Krishna Manikandan <quic_mkrishn@quicinc.com>
12 $ref: /schemas/display/msm/dpu-common.yaml#
17       - qcom,sdm670-dpu
18       - qcom,sdm845-dpu
22       - description: Address offset and size for mdp register set
23       - description: Address offset and size for vbif register set
25   reg-names:
27       - const: mdp
28       - const: vbif
32       - description: Display GCC bus clock
33       - description: Display ahb clock
34       - description: Display axi clock
35       - description: Display core clock
36       - description: Display vsync clock
38   clock-names:
40       - const: gcc-bus
41       - const: iface
42       - const: bus
43       - const: core
44       - const: vsync
47   - compatible
48   - reg
49   - reg-names
50   - clocks
51   - clock-names
56   - |
57     #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
58     #include <dt-bindings/clock/qcom,gcc-sdm845.h>
59     #include <dt-bindings/power/qcom-rpmpd.h>
61     display-controller@ae01000 {
62         compatible = "qcom,sdm845-dpu";
65         reg-names = "mdp", "vbif";
68                  <&dispcc DISP_CC_MDSS_AHB_CLK>,
69                  <&dispcc DISP_CC_MDSS_AXI_CLK>,
70                  <&dispcc DISP_CC_MDSS_MDP_CLK>,
71                  <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
72         clock-names = "gcc-bus", "iface", "bus", "core", "vsync";
74         interrupt-parent = <&mdss>;
76         power-domains = <&rpmhpd SDM845_CX>;
77         operating-points-v2 = <&mdp_opp_table>;
80             #address-cells = <1>;
81             #size-cells = <0>;
86                     remote-endpoint = <&dsi0_in>;
93                     remote-endpoint = <&dsi1_in>;