Lines Matching +full:0 +full:x0ae96a00
42 "^display-controller@[0-9a-f]+$":
50 "^displayport-controller@[0-9a-f]+$":
58 "^dsi@[0-9a-f]+$":
67 "^phy@[0-9a-f]+$":
91 reg = <0x0ae00000 0x1000>;
103 interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mem_noc SLAVE_EBI_CH0 0>,
104 <&mmss_noc MASTER_MDP_PORT1 0 &mem_noc SLAVE_EBI_CH0 0>;
107 iommus = <&apps_smmu 0x880 0x8>,
108 <&apps_smmu 0xc80 0x8>;
116 reg = <0x0ae01000 0x8f000>,
117 <0x0aeb0000 0x2008>;
128 interrupts = <0>;
134 #size-cells = <0>;
136 port@0 {
137 reg = <0>;
154 reg = <0x0ae94000 0x400>;
174 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
183 #size-cells = <0>;
187 #size-cells = <0>;
189 port@0 {
190 reg = <0>;
206 reg = <0x0ae94400 0x200>,
207 <0x0ae94600 0x280>,
208 <0x0ae94a00 0x1e0>;
214 #phy-cells = <0>;
224 reg = <0x0ae96000 0x400>;
244 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
253 #size-cells = <0>;
257 #size-cells = <0>;
259 port@0 {
260 reg = <0>;
276 reg = <0x0ae96400 0x200>,
277 <0x0ae96600 0x280>,
278 <0x0ae96a00 0x10e>;
284 #phy-cells = <0>;