Lines Matching +full:dsi +full:- +full:to +full:- +full:edp
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sc7280-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
17 $ref: /schemas/display/msm/mdss-common.yaml#
21 const: qcom,sc7280-mdss
25 - description: Display AHB clock from gcc
26 - description: Display AHB clock from dispcc
27 - description: Display core clock
29 clock-names:
31 - const: iface
32 - const: ahb
33 - const: core
40 - description: Interconnect path from mdp0 port to the data bus
41 - description: Interconnect path from CPU to the reg bus
43 interconnect-names:
45 - const: mdp0-mem
46 - const: cpu-cfg
49 "^display-controller@[0-9a-f]+$":
55 const: qcom,sc7280-dpu
57 "^displayport-controller@[0-9a-f]+$":
63 const: qcom,sc7280-dp
65 "^dsi@[0-9a-f]+$":
72 - const: qcom,sc7280-dsi-ctrl
73 - const: qcom,mdss-dsi-ctrl
75 "^edp@[0-9a-f]+$":
81 const: qcom,sc7280-edp
83 "^phy@[0-9a-f]+$":
90 - qcom,sc7280-dsi-phy-7nm
91 - qcom,sc7280-edp-phy
94 - compatible
99 - |
100 #include <dt-bindings/clock/qcom,dispcc-sc7280.h>
101 #include <dt-bindings/clock/qcom,gcc-sc7280.h>
102 #include <dt-bindings/clock/qcom,rpmh.h>
103 #include <dt-bindings/interrupt-controller/arm-gic.h>
104 #include <dt-bindings/interconnect/qcom,sc7280.h>
105 #include <dt-bindings/power/qcom-rpmpd.h>
107 display-subsystem@ae00000 {
108 #address-cells = <1>;
109 #size-cells = <1>;
110 compatible = "qcom,sc7280-mdss";
112 reg-names = "mdss";
113 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>;
117 clock-names = "iface",
122 interrupt-controller;
123 #interrupt-cells = <1>;
127 interconnect-names = "mdp0-mem",
128 "cpu-cfg";
133 display-controller@ae01000 {
134 compatible = "qcom,sc7280-dpu";
138 reg-names = "mdp", "vbif";
146 clock-names = "bus",
153 interrupt-parent = <&mdss>;
155 power-domains = <&rpmhpd SC7280_CX>;
156 operating-points-v2 = <&mdp_opp_table>;
159 #address-cells = <1>;
160 #size-cells = <0>;
165 remote-endpoint = <&dsi0_in>;
172 remote-endpoint = <&edp_in>;
179 remote-endpoint = <&dp_in>;
185 dsi@ae94000 {
186 compatible = "qcom,sc7280-dsi-ctrl", "qcom,mdss-dsi-ctrl";
188 reg-names = "dsi_ctrl";
190 interrupt-parent = <&mdss>;
199 clock-names = "byte",
206 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
208 assigned-clock-parents = <&mdss_dsi_phy 0>, <&mdss_dsi_phy 1>;
210 operating-points-v2 = <&dsi_opp_table>;
211 power-domains = <&rpmhpd SC7280_CX>;
214 phy-names = "dsi";
216 #address-cells = <1>;
217 #size-cells = <0>;
220 #address-cells = <1>;
221 #size-cells = <0>;
226 remote-endpoint = <&dpu_intf1_out>;
237 dsi_opp_table: opp-table {
238 compatible = "operating-points-v2";
240 opp-187500000 {
241 opp-hz = /bits/ 64 <187500000>;
242 required-opps = <&rpmhpd_opp_low_svs>;
245 opp-300000000 {
246 opp-hz = /bits/ 64 <300000000>;
247 required-opps = <&rpmhpd_opp_svs>;
250 opp-358000000 {
251 opp-hz = /bits/ 64 <358000000>;
252 required-opps = <&rpmhpd_opp_svs_l1>;
258 compatible = "qcom,sc7280-dsi-phy-7nm";
262 reg-names = "dsi_phy",
266 #clock-cells = <1>;
267 #phy-cells = <0>;
271 clock-names = "iface", "ref";
273 vdds-supply = <&vreg_dsi_supply>;
276 edp@aea0000 {
277 compatible = "qcom,sc7280-edp";
278 pinctrl-names = "default";
279 pinctrl-0 = <&edp_hot_plug_det>;
286 interrupt-parent = <&mdss>;
294 clock-names = "core_iface",
299 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>,
301 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>;
304 phy-names = "dp";
306 operating-points-v2 = <&edp_opp_table>;
307 power-domains = <&rpmhpd SC7280_CX>;
310 #address-cells = <1>;
311 #size-cells = <0>;
316 remote-endpoint = <&dpu_intf5_out>;
326 edp_opp_table: opp-table {
327 compatible = "operating-points-v2";
329 opp-160000000 {
330 opp-hz = /bits/ 64 <160000000>;
331 required-opps = <&rpmhpd_opp_low_svs>;
334 opp-270000000 {
335 opp-hz = /bits/ 64 <270000000>;
336 required-opps = <&rpmhpd_opp_svs>;
339 opp-540000000 {
340 opp-hz = /bits/ 64 <540000000>;
341 required-opps = <&rpmhpd_opp_nom>;
344 opp-810000000 {
345 opp-hz = /bits/ 64 <810000000>;
346 required-opps = <&rpmhpd_opp_nom>;
352 compatible = "qcom,sc7280-edp-phy";
361 clock-names = "aux",
364 #clock-cells = <1>;
365 #phy-cells = <0>;
368 displayport-controller@ae90000 {
369 compatible = "qcom,sc7280-dp";
377 interrupt-parent = <&mdss>;
385 clock-names = "core_iface",
390 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
392 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
394 phy-names = "dp";
396 operating-points-v2 = <&dp_opp_table>;
397 power-domains = <&rpmhpd SC7280_CX>;
399 #sound-dai-cells = <0>;
402 #address-cells = <1>;
403 #size-cells = <0>;
408 remote-endpoint = <&dpu_intf0_out>;
418 dp_opp_table: opp-table {
419 compatible = "operating-points-v2";
421 opp-160000000 {
422 opp-hz = /bits/ 64 <160000000>;
423 required-opps = <&rpmhpd_opp_low_svs>;
426 opp-270000000 {
427 opp-hz = /bits/ 64 <270000000>;
428 required-opps = <&rpmhpd_opp_svs>;
431 opp-540000000 {
432 opp-hz = /bits/ 64 <540000000>;
433 required-opps = <&rpmhpd_opp_svs_l1>;
436 opp-810000000 {
437 opp-hz = /bits/ 64 <810000000>;
438 required-opps = <&rpmhpd_opp_nom>;