Lines Matching +full:0 +full:xaec2200
49 "^display-controller@[0-9a-f]+$":
57 "^displayport-controller@[0-9a-f]+$":
65 "^dsi@[0-9a-f]+$":
75 "^edp@[0-9a-f]+$":
83 "^phy@[0-9a-f]+$":
111 reg = <0xae00000 0x1000>;
130 iommus = <&apps_smmu 0x900 0x402>;
135 reg = <0x0ae01000 0x8f000>,
136 <0x0aeb0000 0x2008>;
154 interrupts = <0>;
160 #size-cells = <0>;
162 port@0 {
163 reg = <0>;
187 reg = <0x0ae94000 0x400>;
208 assigned-clock-parents = <&mdss_dsi_phy 0>, <&mdss_dsi_phy 1>;
217 #size-cells = <0>;
221 #size-cells = <0>;
223 port@0 {
224 reg = <0>;
259 reg = <0x0ae94400 0x200>,
260 <0x0ae94600 0x280>,
261 <0x0ae94900 0x280>;
267 #phy-cells = <0>;
279 pinctrl-0 = <&edp_hot_plug_det>;
281 reg = <0xaea0000 0x200>,
282 <0xaea0200 0x200>,
283 <0xaea0400 0xc00>,
284 <0xaea1000 0x400>;
301 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>;
311 #size-cells = <0>;
313 port@0 {
314 reg = <0>;
354 reg = <0xaec2a00 0x19c>,
355 <0xaec2200 0xa0>,
356 <0xaec2600 0xa0>,
357 <0xaec2000 0x1c0>;
365 #phy-cells = <0>;
371 reg = <0xae90000 0x200>,
372 <0xae90200 0x200>,
373 <0xae90400 0xc00>,
374 <0xae91000 0x400>,
375 <0xae91400 0x400>;
392 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
399 #sound-dai-cells = <0>;
403 #size-cells = <0>;
405 port@0 {
406 reg = <0>;