Lines Matching +full:dsi +full:- +full:controller
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,msm8998-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
17 $ref: /schemas/display/msm/mdss-common.yaml#
21 const: qcom,msm8998-mdss
25 - description: Display AHB clock
26 - description: Display AXI clock
27 - description: Display core clock
29 clock-names:
31 - const: iface
32 - const: bus
33 - const: core
39 "^display-controller@[0-9a-f]+$":
45 const: qcom,msm8998-dpu
47 "^dsi@[0-9a-f]+$":
54 - const: qcom,msm8998-dsi-ctrl
55 - const: qcom,mdss-dsi-ctrl
57 "^phy@[0-9a-f]+$":
63 const: qcom,dsi-phy-10nm-8998
66 - compatible
71 - |
72 #include <dt-bindings/clock/qcom,mmcc-msm8998.h>
73 #include <dt-bindings/clock/qcom,rpmcc.h>
74 #include <dt-bindings/interrupt-controller/arm-gic.h>
75 #include <dt-bindings/power/qcom-rpmpd.h>
77 display-subsystem@c900000 {
78 compatible = "qcom,msm8998-mdss";
80 reg-names = "mdss";
85 clock-names = "iface", "bus", "core";
87 #address-cells = <1>;
88 #interrupt-cells = <1>;
89 #size-cells = <1>;
92 interrupt-controller;
95 power-domains = <&mmcc MDSS_GDSC>;
98 display-controller@c901000 {
99 compatible = "qcom,msm8998-dpu";
104 reg-names = "mdp", "regdma", "vbif", "vbif_nrt";
111 clock-names = "iface", "bus", "mnoc", "core", "vsync";
113 interrupt-parent = <&mdss>;
115 operating-points-v2 = <&mdp_opp_table>;
116 power-domains = <&rpmpd MSM8998_VDDMX>;
119 #address-cells = <1>;
120 #size-cells = <0>;
125 remote-endpoint = <&dsi0_in>;
132 remote-endpoint = <&dsi1_in>;
138 dsi@c994000 {
139 compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl";
141 reg-names = "dsi_ctrl";
143 interrupt-parent = <&mdss>;
152 clock-names = "byte",
158 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>;
159 assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
161 operating-points-v2 = <&dsi_opp_table>;
162 power-domains = <&rpmpd MSM8998_VDDCX>;
165 phy-names = "dsi";
167 #address-cells = <1>;
168 #size-cells = <0>;
171 #address-cells = <1>;
172 #size-cells = <0>;
177 remote-endpoint = <&dpu_intf1_out>;
190 compatible = "qcom,dsi-phy-10nm-8998";
194 reg-names = "dsi_phy",
198 #clock-cells = <1>;
199 #phy-cells = <0>;
203 clock-names = "iface", "ref";
205 vdds-supply = <&pm8998_l1>;
208 dsi@c996000 {
209 compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl";
211 reg-names = "dsi_ctrl";
213 interrupt-parent = <&mdss>;
222 clock-names = "byte",
228 assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>;
229 assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
231 operating-points-v2 = <&dsi_opp_table>;
232 power-domains = <&rpmpd MSM8998_VDDCX>;
235 phy-names = "dsi";
237 #address-cells = <1>;
238 #size-cells = <0>;
241 #address-cells = <1>;
242 #size-cells = <0>;
247 remote-endpoint = <&dpu_intf2_out>;
260 compatible = "qcom,dsi-phy-10nm-8998";
264 reg-names = "dsi_phy",
268 #clock-cells = <1>;
269 #phy-cells = <0>;
273 clock-names = "iface", "ref";
275 vdds-supply = <&pm8998_l1>;