Lines Matching +full:gcc +full:- +full:msm8916

1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
11 - Rob Clark <robdclark@gmail.com>
15 encapsulates sub-blocks like MDP5, DSI, HDMI, eDP, etc.
19 pattern: "^display-subsystem@[0-9a-f]+$"
23 - qcom,mdss
29 reg-names:
32 - const: mdss_phys
33 - const: vbif_phys
34 - const: vbif_nrt_phys
39 interrupt-controller: true
41 "#interrupt-cells":
44 power-domains:
47 The MDSS power domain provided by GCC
51 - minItems: 3
53 - description: Display abh clock
54 - description: Display axi clock
55 - description: Display vsync clock
56 - description: Display core clock
57 - minItems: 1
59 - description: Display abh clock
60 - description: Display core clock
62 clock-names:
64 - minItems: 3
66 - const: iface
67 - const: bus
68 - const: vsync
69 - const: core
70 - minItems: 1
72 - const: iface
73 - const: core
75 "#address-cells":
78 "#size-cells":
85 - description: MDSS_CORE reset
90 - description: Interconnect path from mdp0 (or a single mdp) port to the data bus
91 - description: Interconnect path from CPU to the reg bus
93 interconnect-names:
96 - const: mdp0-mem
97 - const: cpu-cfg
100 - compatible
101 - reg
102 - reg-names
103 - interrupts
104 - interrupt-controller
105 - "#interrupt-cells"
106 - power-domains
107 - clocks
108 - clock-names
109 - "#address-cells"
110 - "#size-cells"
111 - ranges
114 "^display-controller@[1-9a-f][0-9a-f]*$":
122 "^dsi@[1-9a-f][0-9a-f]*$":
128 const: qcom,mdss-dsi-ctrl
130 "^phy@[1-9a-f][0-9a-f]*$":
136 - qcom,dsi-phy-14nm
137 - qcom,dsi-phy-14nm-660
138 - qcom,dsi-phy-14nm-8953
139 - qcom,dsi-phy-20nm
140 - qcom,dsi-phy-28nm-8226
141 - qcom,dsi-phy-28nm-8937
142 - qcom,dsi-phy-28nm-hpm
143 - qcom,dsi-phy-28nm-hpm-fam-b
144 - qcom,dsi-phy-28nm-lp
145 - qcom,hdmi-phy-8084
146 - qcom,hdmi-phy-8660
147 - qcom,hdmi-phy-8960
148 - qcom,hdmi-phy-8974
149 - qcom,hdmi-phy-8996
151 "^hdmi-tx@[1-9a-f][0-9a-f]*$":
157 - qcom,hdmi-tx-8084
158 - qcom,hdmi-tx-8660
159 - qcom,hdmi-tx-8960
160 - qcom,hdmi-tx-8974
161 - qcom,hdmi-tx-8994
162 - qcom,hdmi-tx-8996
167 - |
168 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
169 #include <dt-bindings/interrupt-controller/arm-gic.h>
170 display-subsystem@1a00000 {
174 reg-names = "mdss_phys", "vbif_phys";
176 power-domains = <&gcc MDSS_GDSC>;
178 clocks = <&gcc GCC_MDSS_AHB_CLK>,
179 <&gcc GCC_MDSS_AXI_CLK>,
180 <&gcc GCC_MDSS_VSYNC_CLK>;
181 clock-names = "iface",
187 interrupt-controller;
188 #interrupt-cells = <1>;
190 #address-cells = <1>;
191 #size-cells = <1>;
194 display-controller@1a01000 {
195 compatible = "qcom,msm8916-mdp5", "qcom,mdp5";
197 reg-names = "mdp_phys";
199 interrupt-parent = <&mdss>;
202 clocks = <&gcc GCC_MDSS_AHB_CLK>,
203 <&gcc GCC_MDSS_AXI_CLK>,
204 <&gcc GCC_MDSS_MDP_CLK>,
205 <&gcc GCC_MDSS_VSYNC_CLK>;
206 clock-names = "iface",
214 #address-cells = <1>;
215 #size-cells = <0>;
220 remote-endpoint = <&dsi0_in>;