Lines Matching +full:gcc +full:- +full:msm8974
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Rob Clark <robdclark@gmail.com>
14 # as a work-around:
20 - qcom,adreno
21 - amd,imageon
23 - compatible
28 - description: |
30 figure out the chip-id.
32 - pattern: '^qcom,adreno-[0-9a-f]{8}$'
33 - const: qcom,adreno
34 - description: |
36 figure out the gpu-id and patch level.
38 - pattern: '^qcom,adreno-[3-7][0-9][0-9]\.[0-9]+$'
39 - const: qcom,adreno
40 - description: |
42 figure out the gpu-id and patch level.
44 - pattern: '^amd,imageon-200\.[0-1]$'
45 - const: amd,imageon
51 clock-names:
59 reg-names:
62 - const: kgsl_3d0_reg_memory
63 - const: cx_mem
64 - const: cx_dbgc
69 interrupt-names:
76 interconnect-names:
79 - const: gfx-mem
80 - const: ocmem
87 $ref: /schemas/types.yaml#/definitions/phandle-array
93 phandles to one or more reserved on-chip SRAM regions.
98 operating-points-v2: true
99 opp-table:
102 power-domains:
105 zap-shader:
109 For a5xx and a6xx devices this node contains a memory-region that
113 memory-region:
116 firmware-name:
120 "#cooling-cells":
123 nvmem-cell-names:
126 nvmem-cells:
138 - compatible
139 - reg
140 - interrupts
145 - if:
149 pattern: '^qcom,adreno-[3-5][0-9][0-9]\.[0-9]+$'
157 clock-names:
160 - const: core
162 - const: iface
164 - const: mem
166 - const: mem_iface
168 - const: alt_mem_iface
170 - const: gfx3d
172 - const: rbbmtimer
174 - const: rbcpr
180 - clocks
181 - clock-names
183 - if:
188 - qcom,adreno-610.0
189 - qcom,adreno-619.1
196 clock-names:
198 - const: core
200 - const: iface
202 - const: mem_iface
204 - const: alt_mem_iface
206 - const: gmu
208 - const: xo
211 reg-names:
214 - const: kgsl_3d0_reg_memory
215 - const: cx_dbgc
218 - clocks
219 - clock-names
225 pattern: '^qcom,adreno-[67][0-9][0-9]\.[0-9]+$'
230 clock-names: false
232 reg-names:
235 - const: kgsl_3d0_reg_memory
236 - const: cx_mem
237 - const: cx_dbgc
240 - |
244 #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
245 #include <dt-bindings/clock/qcom,rpmcc.h>
246 #include <dt-bindings/interrupt-controller/irq.h>
247 #include <dt-bindings/interrupt-controller/arm-gic.h>
250 compatible = "qcom,adreno-330.2", "qcom,adreno";
253 reg-names = "kgsl_3d0_reg_memory";
255 clock-names = "core", "iface", "mem_iface";
261 interrupt-names = "kgsl_3d0_irq";
264 power-domains = <&mmcc OXILICX_GDSC>;
265 operating-points-v2 = <&gpu_opp_table>;
267 #cooling-cells = <2>;
271 compatible = "qcom,msm8974-ocmem";
275 reg-names = "ctrl", "mem";
279 clock-names = "core", "iface";
281 #address-cells = <1>;
282 #size-cells = <1>;
285 gpu_sram: gpu-sram@0 {
289 - |
293 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>
294 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
295 #include <dt-bindings/power/qcom-rpmpd.h>
296 #include <dt-bindings/interrupt-controller/irq.h>
297 #include <dt-bindings/interrupt-controller/arm-gic.h>
298 #include <dt-bindings/interconnect/qcom,sdm845.h>
300 reserved-memory {
301 #address-cells = <2>;
302 #size-cells = <2>;
305 compatible = "shared-dma-pool";
307 no-map;
312 compatible = "qcom,adreno-630.2", "qcom,adreno";
315 reg-names = "kgsl_3d0_reg_memory", "cx_mem";
317 #cooling-cells = <2>;
323 operating-points-v2 = <&gpu_opp_table>;
326 interconnect-names = "gfx-mem";
330 gpu_opp_table: opp-table {
331 compatible = "operating-points-v2";
333 opp-430000000 {
334 opp-hz = /bits/ 64 <430000000>;
335 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
336 opp-peak-kBps = <5412000>;
339 opp-355000000 {
340 opp-hz = /bits/ 64 <355000000>;
341 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
342 opp-peak-kBps = <3072000>;
345 opp-267000000 {
346 opp-hz = /bits/ 64 <267000000>;
347 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
348 opp-peak-kBps = <3072000>;
351 opp-180000000 {
352 opp-hz = /bits/ 64 <180000000>;
353 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
354 opp-peak-kBps = <1804000>;
358 zap-shader {
359 memory-region = <&zap_shader_region>;
360 firmware-name = "qcom/LENOVO/81JL/qcdxkmsuc850.mbn";