Lines Matching +full:dispcc +full:- +full:sdm845

1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dsi-phy-10nm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Krishna Manikandan <quic_mkrishn@quicinc.com>
13   - $ref: dsi-phy-common.yaml#
18       - qcom,dsi-phy-10nm
19       - qcom,dsi-phy-10nm-8998
23       - description: dsi phy register set
24       - description: dsi phy lane register set
25       - description: dsi pll register set
27   reg-names:
29       - const: dsi_phy
30       - const: dsi_phy_lane
31       - const: dsi_pll
33   vdds-supply:
36       connected to VDDA_MIPI_DSI_0_PLL_0P9 pin for sdm845 target
38   qcom,phy-rescode-offset-top:
39     $ref: /schemas/types.yaml#/definitions/int8-array
42       Integer array of offset for pull-up legs rescode for all five lanes.
44       manner, -32 is the weakest and +31 is the strongest.
46       minimum: -32
49   qcom,phy-rescode-offset-bot:
50     $ref: /schemas/types.yaml#/definitions/int8-array
53       Integer array of offset for pull-down legs rescode for all five lanes.
55       manner, -32 is the weakest and +31 is the strongest.
57       minimum: -32
60   qcom,phy-drive-ldo-level:
69   - compatible
70   - reg
71   - reg-names
76   - |
77      #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
78      #include <dt-bindings/clock/qcom,rpmh.h>
80      dsi-phy@ae94400 {
81          compatible = "qcom,dsi-phy-10nm";
85          reg-names = "dsi_phy",
89          #clock-cells = <1>;
90          #phy-cells = <0>;
92          vdds-supply = <&vdda_mipi_dsi0_pll>;
93          clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
95          clock-names = "iface", "ref";
97          qcom,phy-rescode-offset-top = /bits/ 8 <0 0 0 0 0>;
98          qcom,phy-rescode-offset-bot = /bits/ 8 <0 0 0 0 0>;
99          qcom,phy-drive-ldo-level = <400>;