Lines Matching +full:sm6115 +full:- +full:mdss
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
15 - items:
16 - enum:
17 - qcom,apq8064-dsi-ctrl
18 - qcom,msm8226-dsi-ctrl
19 - qcom,msm8916-dsi-ctrl
20 - qcom,msm8953-dsi-ctrl
21 - qcom,msm8974-dsi-ctrl
22 - qcom,msm8976-dsi-ctrl
23 - qcom,msm8996-dsi-ctrl
24 - qcom,msm8998-dsi-ctrl
25 - qcom,qcm2290-dsi-ctrl
26 - qcom,sc7180-dsi-ctrl
27 - qcom,sc7280-dsi-ctrl
28 - qcom,sdm660-dsi-ctrl
29 - qcom,sdm670-dsi-ctrl
30 - qcom,sdm845-dsi-ctrl
31 - qcom,sm6115-dsi-ctrl
32 - qcom,sm6125-dsi-ctrl
33 - qcom,sm6150-dsi-ctrl
34 - qcom,sm6350-dsi-ctrl
35 - qcom,sm6375-dsi-ctrl
36 - qcom,sm7150-dsi-ctrl
37 - qcom,sm8150-dsi-ctrl
38 - qcom,sm8250-dsi-ctrl
39 - qcom,sm8350-dsi-ctrl
40 - qcom,sm8450-dsi-ctrl
41 - qcom,sm8550-dsi-ctrl
42 - qcom,sm8650-dsi-ctrl
43 - const: qcom,mdss-dsi-ctrl
44 - enum:
45 - qcom,dsi-ctrl-6g-qcm2290
46 - qcom,mdss-dsi-ctrl # This should always come with an SoC-specific compatible
52 reg-names:
61 - bus:: Display AHB clock.
62 - byte:: Display byte clock.
63 - byte_intf:: Display byte interface clock.
64 - core:: Display core clock.
65 - core_mss:: Core MultiMedia SubSystem clock.
66 - iface:: Display AXI clock.
67 - mdp_core:: MDP Core clock.
68 - mnoc:: MNOC clock
69 - pixel:: Display pixel clock.
73 clock-names:
80 phy-names:
84 syscon-sfpb:
88 qcom,dual-dsi-mode:
94 qcom,master-dsi:
98 qcom,dual-dsi-mode enabled.
100 qcom,sync-dual-dsi:
104 with MIPI DCS commands when qcom,dual-dsi-mode enabled.
106 assigned-clocks:
114 assigned-clock-parents:
120 power-domains:
123 operating-points-v2: true
125 opp-table:
136 $ref: /schemas/graph.yaml#/$defs/port-base
142 $ref: /schemas/media/video-interfaces.yaml#
145 data-lanes:
152 $ref: /schemas/graph.yaml#/$defs/port-base
158 $ref: /schemas/media/video-interfaces.yaml#
161 data-lanes:
167 qcom,te-source:
174 - mdp_vsync_p
175 - mdp_vsync_s
176 - mdp_vsync_e
177 - timer0
178 - timer1
179 - timer2
180 - timer3
181 - timer4
184 - port@0
185 - port@1
187 avdd-supply:
191 refgen-supply:
195 vcca-supply:
199 vdd-supply:
203 vddio-supply:
205 VDD-IO regulator
207 vdda-supply:
212 - compatible
213 - reg
214 - reg-names
215 - interrupts
216 - clocks
217 - clock-names
218 - phys
219 - assigned-clocks
220 - assigned-clock-parents
221 - ports
224 - $ref: ../dsi-controller.yaml#
225 - if:
230 - qcom,apq8064-dsi-ctrl
235 clock-names:
237 - const: iface
238 - const: bus
239 - const: core_mmss
240 - const: src
241 - const: byte
242 - const: pixel
243 - const: core
245 - if:
250 - qcom,msm8916-dsi-ctrl
255 clock-names:
257 - const: mdp_core
258 - const: iface
259 - const: bus
260 - const: byte
261 - const: pixel
262 - const: core
264 - if:
269 - qcom,msm8953-dsi-ctrl
270 - qcom,msm8976-dsi-ctrl
275 clock-names:
277 - const: mdp_core
278 - const: iface
279 - const: bus
280 - const: byte
281 - const: pixel
282 - const: core
284 - if:
289 - qcom,msm8226-dsi-ctrl
290 - qcom,msm8974-dsi-ctrl
295 clock-names:
297 - const: mdp_core
298 - const: iface
299 - const: bus
300 - const: byte
301 - const: pixel
302 - const: core
303 - const: core_mmss
305 - if:
310 - qcom,msm8996-dsi-ctrl
315 clock-names:
317 - const: mdp_core
318 - const: byte
319 - const: iface
320 - const: bus
321 - const: core_mmss
322 - const: pixel
323 - const: core
325 - if:
330 - qcom,msm8998-dsi-ctrl
331 - qcom,sm6125-dsi-ctrl
332 - qcom,sm6350-dsi-ctrl
337 clock-names:
339 - const: byte
340 - const: byte_intf
341 - const: pixel
342 - const: core
343 - const: iface
344 - const: bus
346 - if:
351 - qcom,sc7180-dsi-ctrl
352 - qcom,sc7280-dsi-ctrl
353 - qcom,sm6150-dsi-ctrl
354 - qcom,sm7150-dsi-ctrl
355 - qcom,sm8150-dsi-ctrl
356 - qcom,sm8250-dsi-ctrl
357 - qcom,sm8350-dsi-ctrl
358 - qcom,sm8450-dsi-ctrl
359 - qcom,sm8550-dsi-ctrl
360 - qcom,sm8650-dsi-ctrl
365 clock-names:
367 - const: byte
368 - const: byte_intf
369 - const: pixel
370 - const: core
371 - const: iface
372 - const: bus
374 - if:
379 - qcom,sdm660-dsi-ctrl
384 clock-names:
386 - const: mdp_core
387 - const: byte
388 - const: byte_intf
389 - const: mnoc
390 - const: iface
391 - const: bus
392 - const: core_mmss
393 - const: pixel
394 - const: core
396 - if:
401 - qcom,sdm845-dsi-ctrl
402 - qcom,sm6115-dsi-ctrl
403 - qcom,sm6375-dsi-ctrl
408 clock-names:
410 - const: byte
411 - const: byte_intf
412 - const: pixel
413 - const: core
414 - const: iface
415 - const: bus
420 - |
421 #include <dt-bindings/interrupt-controller/arm-gic.h>
422 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
423 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
424 #include <dt-bindings/power/qcom-rpmpd.h>
427 compatible = "qcom,sc7180-dsi-ctrl", "qcom,mdss-dsi-ctrl";
429 reg-names = "dsi_ctrl";
431 #address-cells = <1>;
432 #size-cells = <0>;
434 interrupt-parent = <&mdss>;
443 clock-names = "byte",
451 phy-names = "dsi";
453 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
454 assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;
456 power-domains = <&rpmhpd SC7180_CX>;
457 operating-points-v2 = <&dsi_opp_table>;
460 #address-cells = <1>;
461 #size-cells = <0>;
466 remote-endpoint = <&dpu_intf1_out>;
473 remote-endpoint = <&sn65dsi86_in>;
474 data-lanes = <0 1 2 3>;
475 qcom,te-source = "mdp_vsync_e";