Lines Matching +full:gcc +full:- +full:apq8064
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
15 - items:
16 - enum:
17 - qcom,apq8064-dsi-ctrl
18 - qcom,msm8226-dsi-ctrl
19 - qcom,msm8916-dsi-ctrl
20 - qcom,msm8953-dsi-ctrl
21 - qcom,msm8974-dsi-ctrl
22 - qcom,msm8976-dsi-ctrl
23 - qcom,msm8996-dsi-ctrl
24 - qcom,msm8998-dsi-ctrl
25 - qcom,qcm2290-dsi-ctrl
26 - qcom,sa8775p-dsi-ctrl
27 - qcom,sar2130p-dsi-ctrl
28 - qcom,sc7180-dsi-ctrl
29 - qcom,sc7280-dsi-ctrl
30 - qcom,sdm660-dsi-ctrl
31 - qcom,sdm670-dsi-ctrl
32 - qcom,sdm845-dsi-ctrl
33 - qcom,sm6115-dsi-ctrl
34 - qcom,sm6125-dsi-ctrl
35 - qcom,sm6150-dsi-ctrl
36 - qcom,sm6350-dsi-ctrl
37 - qcom,sm6375-dsi-ctrl
38 - qcom,sm7150-dsi-ctrl
39 - qcom,sm8150-dsi-ctrl
40 - qcom,sm8250-dsi-ctrl
41 - qcom,sm8350-dsi-ctrl
42 - qcom,sm8450-dsi-ctrl
43 - qcom,sm8550-dsi-ctrl
44 - qcom,sm8650-dsi-ctrl
45 - qcom,sm8750-dsi-ctrl
46 - const: qcom,mdss-dsi-ctrl
47 - enum:
48 - qcom,dsi-ctrl-6g-qcm2290
49 - qcom,mdss-dsi-ctrl # This should always come with an SoC-specific compatible
55 reg-names:
64 - bus:: Display AHB clock.
65 - byte:: Display byte clock.
66 - byte_intf:: Display byte interface clock.
67 - core:: Display core clock.
68 - core_mss:: Core MultiMedia SubSystem clock.
69 - iface:: Display AXI clock.
70 - mdp_core:: MDP Core clock.
71 - mnoc:: MNOC clock
72 - pixel:: Display pixel clock.
76 clock-names:
83 phy-names:
87 syscon-sfpb:
91 qcom,dual-dsi-mode:
97 qcom,master-dsi:
101 qcom,dual-dsi-mode enabled.
103 qcom,sync-dual-dsi:
107 with MIPI DCS commands when qcom,dual-dsi-mode enabled.
109 assigned-clocks:
118 assigned-clock-parents:
124 power-domains:
127 operating-points-v2: true
129 opp-table:
140 $ref: /schemas/graph.yaml#/$defs/port-base
146 $ref: /schemas/media/video-interfaces.yaml#
149 data-lanes:
156 $ref: /schemas/graph.yaml#/$defs/port-base
162 $ref: /schemas/media/video-interfaces.yaml#
165 data-lanes:
171 qcom,te-source:
178 - mdp_vsync_p
179 - mdp_vsync_s
180 - mdp_vsync_e
181 - timer0
182 - timer1
183 - timer2
184 - timer3
185 - timer4
188 - port@0
189 - port@1
191 avdd-supply:
195 refgen-supply:
199 vcca-supply:
203 vdd-supply:
207 vddio-supply:
209 VDD-IO regulator
211 vdda-supply:
216 - compatible
217 - reg
218 - reg-names
219 - interrupts
220 - clocks
221 - clock-names
222 - phys
223 - ports
226 - $ref: ../dsi-controller.yaml#
227 - if:
232 - qcom,apq8064-dsi-ctrl
238 clock-names:
240 - const: iface
241 - const: bus
242 - const: core_mmss
243 - const: src
244 - const: byte
245 - const: pixel
246 - const: core
248 - assigned-clocks
249 - assigned-clock-parents
251 - if:
256 - qcom,msm8916-dsi-ctrl
257 - qcom,msm8953-dsi-ctrl
258 - qcom,msm8976-dsi-ctrl
264 clock-names:
266 - const: mdp_core
267 - const: iface
268 - const: bus
269 - const: byte
270 - const: pixel
271 - const: core
273 - assigned-clocks
274 - assigned-clock-parents
276 - if:
281 - qcom,msm8226-dsi-ctrl
282 - qcom,msm8974-dsi-ctrl
288 clock-names:
290 - const: mdp_core
291 - const: iface
292 - const: bus
293 - const: byte
294 - const: pixel
295 - const: core
296 - const: core_mmss
298 - assigned-clocks
299 - assigned-clock-parents
301 - if:
306 - qcom,msm8996-dsi-ctrl
312 clock-names:
314 - const: mdp_core
315 - const: byte
316 - const: iface
317 - const: bus
318 - const: core_mmss
319 - const: pixel
320 - const: core
322 - assigned-clocks
323 - assigned-clock-parents
325 - if:
330 - qcom,msm8998-dsi-ctrl
331 - qcom,sa8775p-dsi-ctrl
332 - qcom,sar2130p-dsi-ctrl
333 - qcom,sc7180-dsi-ctrl
334 - qcom,sc7280-dsi-ctrl
335 - qcom,sdm845-dsi-ctrl
336 - qcom,sm6115-dsi-ctrl
337 - qcom,sm6125-dsi-ctrl
338 - qcom,sm6350-dsi-ctrl
339 - qcom,sm6375-dsi-ctrl
340 - qcom,sm6150-dsi-ctrl
341 - qcom,sm7150-dsi-ctrl
342 - qcom,sm8150-dsi-ctrl
343 - qcom,sm8250-dsi-ctrl
344 - qcom,sm8350-dsi-ctrl
345 - qcom,sm8450-dsi-ctrl
346 - qcom,sm8550-dsi-ctrl
347 - qcom,sm8650-dsi-ctrl
353 clock-names:
355 - const: byte
356 - const: byte_intf
357 - const: pixel
358 - const: core
359 - const: iface
360 - const: bus
362 - assigned-clocks
363 - assigned-clock-parents
365 - if:
370 - qcom,sm8750-dsi-ctrl
376 clock-names:
378 - const: byte
379 - const: byte_intf
380 - const: pixel
381 - const: core
382 - const: iface
383 - const: bus
384 - const: dsi_pll_pixel
385 - const: dsi_pll_byte
386 - const: esync
387 - const: osc
388 - const: byte_src
389 - const: pixel_src
391 - if:
396 - qcom,sdm660-dsi-ctrl
402 clock-names:
404 - const: mdp_core
405 - const: byte
406 - const: byte_intf
407 - const: mnoc
408 - const: iface
409 - const: bus
410 - const: core_mmss
411 - const: pixel
412 - const: core
414 - assigned-clocks
415 - assigned-clock-parents
420 - |
421 #include <dt-bindings/interrupt-controller/arm-gic.h>
422 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
423 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
424 #include <dt-bindings/power/qcom-rpmpd.h>
427 compatible = "qcom,sc7180-dsi-ctrl", "qcom,mdss-dsi-ctrl";
429 reg-names = "dsi_ctrl";
431 #address-cells = <1>;
432 #size-cells = <0>;
434 interrupt-parent = <&mdss>;
443 clock-names = "byte",
451 phy-names = "dsi";
453 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
454 assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;
456 power-domains = <&rpmhpd SC7180_CX>;
457 operating-points-v2 = <&dsi_opp_table>;
460 #address-cells = <1>;
461 #size-cells = <0>;
466 remote-endpoint = <&dpu_intf1_out>;
473 remote-endpoint = <&sn65dsi86_in>;
474 data-lanes = <0 1 2 3>;
475 qcom,te-source = "mdp_vsync_e";