Lines Matching +full:dispcc +full:- +full:sm8350
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
15 - items:
16 - enum:
17 - qcom,apq8064-dsi-ctrl
18 - qcom,msm8226-dsi-ctrl
19 - qcom,msm8916-dsi-ctrl
20 - qcom,msm8953-dsi-ctrl
21 - qcom,msm8974-dsi-ctrl
22 - qcom,msm8976-dsi-ctrl
23 - qcom,msm8996-dsi-ctrl
24 - qcom,msm8998-dsi-ctrl
25 - qcom,qcm2290-dsi-ctrl
26 - qcom,sc7180-dsi-ctrl
27 - qcom,sc7280-dsi-ctrl
28 - qcom,sdm660-dsi-ctrl
29 - qcom,sdm670-dsi-ctrl
30 - qcom,sdm845-dsi-ctrl
31 - qcom,sm6115-dsi-ctrl
32 - qcom,sm6125-dsi-ctrl
33 - qcom,sm6350-dsi-ctrl
34 - qcom,sm6375-dsi-ctrl
35 - qcom,sm7150-dsi-ctrl
36 - qcom,sm8150-dsi-ctrl
37 - qcom,sm8250-dsi-ctrl
38 - qcom,sm8350-dsi-ctrl
39 - qcom,sm8450-dsi-ctrl
40 - qcom,sm8550-dsi-ctrl
41 - qcom,sm8650-dsi-ctrl
42 - const: qcom,mdss-dsi-ctrl
43 - enum:
44 - qcom,dsi-ctrl-6g-qcm2290
45 - qcom,mdss-dsi-ctrl # This should always come with an SoC-specific compatible
51 reg-names:
60 - bus:: Display AHB clock.
61 - byte:: Display byte clock.
62 - byte_intf:: Display byte interface clock.
63 - core:: Display core clock.
64 - core_mss:: Core MultiMedia SubSystem clock.
65 - iface:: Display AXI clock.
66 - mdp_core:: MDP Core clock.
67 - mnoc:: MNOC clock
68 - pixel:: Display pixel clock.
72 clock-names:
79 phy-names:
83 syscon-sfpb:
87 qcom,dual-dsi-mode:
93 qcom,master-dsi:
97 qcom,dual-dsi-mode enabled.
99 qcom,sync-dual-dsi:
103 with MIPI DCS commands when qcom,dual-dsi-mode enabled.
105 assigned-clocks:
113 assigned-clock-parents:
119 power-domains:
122 operating-points-v2: true
124 opp-table:
135 $ref: /schemas/graph.yaml#/$defs/port-base
141 $ref: /schemas/media/video-interfaces.yaml#
144 data-lanes:
151 $ref: /schemas/graph.yaml#/$defs/port-base
157 $ref: /schemas/media/video-interfaces.yaml#
160 data-lanes:
166 qcom,te-source:
173 - mdp_vsync_p
174 - mdp_vsync_s
175 - mdp_vsync_e
176 - timer0
177 - timer1
178 - timer2
179 - timer3
180 - timer4
183 - port@0
184 - port@1
186 avdd-supply:
190 refgen-supply:
194 vcca-supply:
198 vdd-supply:
202 vddio-supply:
204 VDD-IO regulator
206 vdda-supply:
211 - compatible
212 - reg
213 - reg-names
214 - interrupts
215 - clocks
216 - clock-names
217 - phys
218 - assigned-clocks
219 - assigned-clock-parents
220 - ports
223 - $ref: ../dsi-controller.yaml#
224 - if:
229 - qcom,apq8064-dsi-ctrl
234 clock-names:
236 - const: iface
237 - const: bus
238 - const: core_mmss
239 - const: src
240 - const: byte
241 - const: pixel
242 - const: core
244 - if:
249 - qcom,msm8916-dsi-ctrl
254 clock-names:
256 - const: mdp_core
257 - const: iface
258 - const: bus
259 - const: byte
260 - const: pixel
261 - const: core
263 - if:
268 - qcom,msm8953-dsi-ctrl
269 - qcom,msm8976-dsi-ctrl
274 clock-names:
276 - const: mdp_core
277 - const: iface
278 - const: bus
279 - const: byte
280 - const: pixel
281 - const: core
283 - if:
288 - qcom,msm8226-dsi-ctrl
289 - qcom,msm8974-dsi-ctrl
294 clock-names:
296 - const: mdp_core
297 - const: iface
298 - const: bus
299 - const: byte
300 - const: pixel
301 - const: core
302 - const: core_mmss
304 - if:
309 - qcom,msm8996-dsi-ctrl
314 clock-names:
316 - const: mdp_core
317 - const: byte
318 - const: iface
319 - const: bus
320 - const: core_mmss
321 - const: pixel
322 - const: core
324 - if:
329 - qcom,msm8998-dsi-ctrl
330 - qcom,sm6125-dsi-ctrl
331 - qcom,sm6350-dsi-ctrl
336 clock-names:
338 - const: byte
339 - const: byte_intf
340 - const: pixel
341 - const: core
342 - const: iface
343 - const: bus
345 - if:
350 - qcom,sc7180-dsi-ctrl
351 - qcom,sc7280-dsi-ctrl
352 - qcom,sm7150-dsi-ctrl
353 - qcom,sm8150-dsi-ctrl
354 - qcom,sm8250-dsi-ctrl
355 - qcom,sm8350-dsi-ctrl
356 - qcom,sm8450-dsi-ctrl
357 - qcom,sm8550-dsi-ctrl
358 - qcom,sm8650-dsi-ctrl
363 clock-names:
365 - const: byte
366 - const: byte_intf
367 - const: pixel
368 - const: core
369 - const: iface
370 - const: bus
372 - if:
377 - qcom,sdm660-dsi-ctrl
382 clock-names:
384 - const: mdp_core
385 - const: byte
386 - const: byte_intf
387 - const: mnoc
388 - const: iface
389 - const: bus
390 - const: core_mmss
391 - const: pixel
392 - const: core
394 - if:
399 - qcom,sdm845-dsi-ctrl
400 - qcom,sm6115-dsi-ctrl
401 - qcom,sm6375-dsi-ctrl
406 clock-names:
408 - const: byte
409 - const: byte_intf
410 - const: pixel
411 - const: core
412 - const: iface
413 - const: bus
418 - |
419 #include <dt-bindings/interrupt-controller/arm-gic.h>
420 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
421 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
422 #include <dt-bindings/power/qcom-rpmpd.h>
425 compatible = "qcom,sc7180-dsi-ctrl", "qcom,mdss-dsi-ctrl";
427 reg-names = "dsi_ctrl";
429 #address-cells = <1>;
430 #size-cells = <0>;
432 interrupt-parent = <&mdss>;
435 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
436 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
437 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
438 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
439 <&dispcc DISP_CC_MDSS_AHB_CLK>,
440 <&dispcc DISP_CC_MDSS_AXI_CLK>;
441 clock-names = "byte",
449 phy-names = "dsi";
451 … assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
452 assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;
454 power-domains = <&rpmhpd SC7180_CX>;
455 operating-points-v2 = <&dsi_opp_table>;
458 #address-cells = <1>;
459 #size-cells = <0>;
464 remote-endpoint = <&dpu_intf1_out>;
471 remote-endpoint = <&sn65dsi86_in>;
472 data-lanes = <0 1 2 3>;
473 qcom,te-source = "mdp_vsync_e";