Lines Matching +full:sm6350 +full:- +full:dispcc
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kuogee Hsieh <quic_khsieh@quicinc.com>
19 - enum:
20 - qcom,sc7180-dp
21 - qcom,sc7280-dp
22 - qcom,sc7280-edp
23 - qcom,sc8180x-dp
24 - qcom,sc8180x-edp
25 - qcom,sc8280xp-dp
26 - qcom,sc8280xp-edp
27 - qcom,sdm845-dp
28 - qcom,sm8350-dp
29 - qcom,sm8650-dp
30 - items:
31 - enum:
32 - qcom,sm6350-dp
33 - qcom,sm8150-dp
34 - qcom,sm8250-dp
35 - qcom,sm8450-dp
36 - qcom,sm8550-dp
37 - const: qcom,sm8350-dp
42 - description: ahb register block
43 - description: aux register block
44 - description: link register block
45 - description: p0 register block
46 - description: p1 register block
53 - description: AHB clock to enable register access
54 - description: Display Port AUX clock
55 - description: Display Port Link clock
56 - description: Link interface clock between DP and PHY
57 - description: Display Port Pixel clock
59 clock-names:
61 - const: core_iface
62 - const: core_aux
63 - const: ctrl_link
64 - const: ctrl_link_iface
65 - const: stream_pixel
67 assigned-clocks:
69 - description: link clock source
70 - description: pixel clock source
72 assigned-clock-parents:
74 - description: phy 0 parent
75 - description: phy 1 parent
80 phy-names:
82 - const: dp
84 operating-points-v2: true
86 opp-table:
89 power-domains:
92 aux-bus:
93 $ref: /schemas/display/dp-aux-bus.yaml#
95 data-lanes:
96 $ref: /schemas/types.yaml#/definitions/uint32-array
103 "#sound-dai-cells":
106 vdda-0p9-supply:
108 vdda-1p2-supply:
119 $ref: /schemas/graph.yaml#/$defs/port-base
124 $ref: /schemas/media/video-interfaces.yaml#
127 data-lanes:
133 link-frequencies:
140 - port@0
141 - port@1
144 - compatible
145 - reg
146 - interrupts
147 - clocks
148 - clock-names
149 - phys
150 - phy-names
151 - power-domains
152 - ports
158 - if:
163 - qcom,sc7280-edp
164 - qcom,sc8180x-edp
165 - qcom,sc8280xp-edp
168 "#sound-dai-cells": false
171 aux-bus: false
175 - "#sound-dai-cells"
180 - |
181 #include <dt-bindings/interrupt-controller/arm-gic.h>
182 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
183 #include <dt-bindings/power/qcom-rpmpd.h>
185 displayport-controller@ae90000 {
186 compatible = "qcom,sc7180-dp";
192 interrupt-parent = <&mdss>;
194 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
195 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
196 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
197 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
198 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
199 clock-names = "core_iface", "core_aux",
203 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
204 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
206 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
209 phy-names = "dp";
211 #sound-dai-cells = <0>;
213 power-domains = <&rpmhpd SC7180_CX>;
216 #address-cells = <1>;
217 #size-cells = <0>;
222 remote-endpoint = <&dpu_intf0_out>;
229 remote-endpoint = <&typec>;
230 data-lanes = <0 1>;
231 link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;