Lines Matching +full:aux +full:- +full:output +full:- +full:power
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kuogee Hsieh <quic_khsieh@quicinc.com>
11 - Abhinav Kumar <quic_abhinavk@quicinc.com>
20 - enum:
21 - qcom,sa8775p-dp
22 - qcom,sc7180-dp
23 - qcom,sc7280-dp
24 - qcom,sc7280-edp
25 - qcom,sc8180x-dp
26 - qcom,sc8180x-edp
27 - qcom,sc8280xp-dp
28 - qcom,sc8280xp-edp
29 - qcom,sdm845-dp
30 - qcom,sm8350-dp
31 - qcom,sm8650-dp
32 - items:
33 - enum:
34 - qcom,sar2130p-dp
35 - qcom,sm6350-dp
36 - qcom,sm8150-dp
37 - qcom,sm8250-dp
38 - qcom,sm8450-dp
39 - qcom,sm8550-dp
40 - const: qcom,sm8350-dp
41 - items:
42 - enum:
43 - qcom,sm8750-dp
44 - const: qcom,sm8650-dp
49 - description: ahb register block
50 - description: aux register block
51 - description: link register block
52 - description: p0 register block
53 - description: p1 register block
60 - description: AHB clock to enable register access
61 - description: Display Port AUX clock
62 - description: Display Port Link clock
63 - description: Link interface clock between DP and PHY
64 - description: Display Port Pixel clock
66 clock-names:
68 - const: core_iface
69 - const: core_aux
70 - const: ctrl_link
71 - const: ctrl_link_iface
72 - const: stream_pixel
74 assigned-clocks:
76 - description: link clock source
77 - description: pixel clock source
79 assigned-clock-parents:
81 - description: phy 0 parent
82 - description: phy 1 parent
87 phy-names:
89 - const: dp
91 operating-points-v2: true
93 opp-table:
96 power-domains:
99 aux-bus:
100 $ref: /schemas/display/dp-aux-bus.yaml#
102 data-lanes:
103 $ref: /schemas/types.yaml#/definitions/uint32-array
110 "#sound-dai-cells":
113 vdda-0p9-supply:
115 vdda-1p2-supply:
126 $ref: /schemas/graph.yaml#/$defs/port-base
128 description: Output endpoint of the controller
131 $ref: /schemas/media/video-interfaces.yaml#
134 data-lanes:
140 link-frequencies:
147 - port@0
148 - port@1
151 - compatible
152 - reg
153 - interrupts
154 - clocks
155 - clock-names
156 - phys
157 - phy-names
158 - power-domains
159 - ports
162 # AUX BUS does not exist on DP controllers
163 # Audio output also is present only on DP output
165 - if:
170 - qcom,sc7280-edp
171 - qcom,sc8180x-edp
172 - qcom,sc8280xp-edp
175 "#sound-dai-cells": false
178 aux-bus: false
182 - "#sound-dai-cells"
187 - |
188 #include <dt-bindings/interrupt-controller/arm-gic.h>
189 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
190 #include <dt-bindings/power/qcom-rpmpd.h>
192 displayport-controller@ae90000 {
193 compatible = "qcom,sc7180-dp";
199 interrupt-parent = <&mdss>;
206 clock-names = "core_iface", "core_aux",
210 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
213 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
216 phy-names = "dp";
218 #sound-dai-cells = <0>;
220 power-domains = <&rpmhpd SC7180_CX>;
223 #address-cells = <1>;
224 #size-cells = <0>;
229 remote-endpoint = <&dpu_intf0_out>;
236 remote-endpoint = <&typec>;
237 data-lanes = <0 1>;
238 link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;