Lines Matching +full:mt8188 +full:- +full:power

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - CK Hu <ck.hu@mediatek.com>
11   - Jitao shi <jitao.shi@mediatek.com>
15   subsystem and provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a
21       - enum:
22           - mediatek,mt2701-dpi
23           - mediatek,mt7623-dpi
24           - mediatek,mt8173-dpi
25           - mediatek,mt8183-dpi
26           - mediatek,mt8186-dpi
27           - mediatek,mt8188-dp-intf
28           - mediatek,mt8192-dpi
29           - mediatek,mt8195-dp-intf
30       - items:
31           - enum:
32               - mediatek,mt6795-dpi
33           - const: mediatek,mt8183-dpi
34       - items:
35           - enum:
36               - mediatek,mt8365-dpi
37           - const: mediatek,mt8192-dpi
47       - description: Pixel Clock
48       - description: Engine Clock
49       - description: DPI PLL
51   clock-names:
53       - const: pixel
54       - const: engine
55       - const: pll
57   pinctrl-0: true
58   pinctrl-1: true
60   pinctrl-names:
62       - const: default
63       - const: sleep
65   power-domains:
68       following multimedia power domains:
72       The specific power domain used varies depending on the SoC design.
74       It is recommended to explicitly add the appropriate power domain
97       - port@0
98       - port@1
101   - compatible
102   - reg
103   - interrupts
104   - clocks
105   - clock-names
108   - required:
109       - port
110   - required:
111       - ports
116   - |
117     #include <dt-bindings/interrupt-controller/arm-gic.h>
118     #include <dt-bindings/clock/mt8173-clk.h>
121         compatible = "mediatek,mt8173-dpi";
127         clock-names = "pixel", "engine", "pll";
128         pinctrl-names = "default", "sleep";
129         pinctrl-0 = <&dpi_pin_func>;
130         pinctrl-1 = <&dpi_pin_idle>;
134                 remote-endpoint = <&hdmi0_in>;