Lines Matching +full:mt8188 +full:- +full:power
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11 - Jitao shi <jitao.shi@mediatek.com>
17 In addition, We just need to enable the power domain of DP, so the clock
24 - mediatek,mt8188-dp-tx
25 - mediatek,mt8188-edp-tx
26 - mediatek,mt8195-dp-tx
27 - mediatek,mt8195-edp-tx
32 nvmem-cells:
36 nvmem-cell-names:
39 power-domains:
53 $ref: /schemas/graph.yaml#/$defs/port-base
58 $ref: /schemas/media/video-interfaces.yaml#
61 data-lanes:
65 0 - For 1 lane enabled in IP.
66 0 1 - For 2 lanes enabled in IP.
67 0 1 2 3 - For 4 lanes enabled in IP.
71 - data-lanes
74 - port@0
75 - port@1
77 max-linkrate-mhz:
82 - compatible
83 - reg
84 - interrupts
85 - ports
86 - max-linkrate-mhz
91 - |
92 #include <dt-bindings/interrupt-controller/arm-gic.h>
93 #include <dt-bindings/power/mt8195-power.h>
95 compatible = "mediatek,mt8195-dp-tx";
97 power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>;
99 max-linkrate-mhz = <8100>;
102 #address-cells = <1>;
103 #size-cells = <0>;
108 remote-endpoint = <&dp_intf0_out>;
114 data-lanes = <0 1 2 3>;