Lines Matching +full:lvds +full:- +full:encoder
1 Device-Tree bindings for LVDS Display Bridge (ldb)
3 LVDS Display Bridge
6 The LVDS Display Bridge device tree node contains up to two lvds-channel
7 nodes describing each of the two LVDS encoder channels of the bridge.
10 - #address-cells : should be <1>
11 - #size-cells : should be <0>
12 - compatible : should be "fsl,imx53-ldb" or "fsl,imx6q-ldb".
15 interfaces as input for each LVDS channel.
16 - gpr : should be <&gpr> on i.MX53 and i.MX6q.
17 The phandle points to the iomuxc-gpr region containing the LVDS
19 - clocks, clock-names : phandles to the LDB divider and selector clocks and to
21 Documentation/devicetree/bindings/clock/clock-bindings.txt
23 "di0_pll" - LDB LVDS channel 0 mux
24 "di1_pll" - LDB LVDS channel 1 mux
25 "di0" - LDB LVDS channel 0 gate
26 "di1" - LDB LVDS channel 1 gate
27 "di0_sel" - IPU1 DI0 mux
28 "di1_sel" - IPU1 DI1 mux
30 "di2_sel" - IPU2 DI0 mux
31 "di3_sel" - IPU2 DI1 mux
33 Documentation/devicetree/bindings/clock/imx5-clock.yaml, and in
34 Documentation/devicetree/bindings/clock/imx6q-clock.yaml.
37 - pinctrl-names : should be "default" on i.MX53, not used on i.MX6q
38 - pinctrl-0 : a phandle pointing to LVDS pin settings on i.MX53,
40 - fsl,dual-channel : boolean. if it exists, only LVDS channel 0 should
41 be configured - one input will be distributed on both outputs in dual
44 LVDS Channel
47 Each LVDS Channel has to contain either an of graph link to a panel device node
48 or a display-timings node that describes the video timings for the connected
49 LVDS display as well as the fsl,data-mapping and fsl,data-width properties.
52 - reg : should be <0> or <1>
53 - port: Input and output port nodes with endpoint definitions as defined in
55 On i.MX5, the internal two-input-multiplexer is used. Due to hardware
57 (lvds-channel@[0,1], respectively).
58 On i.MX6, there should be four input ports (port@[0-3]) that correspond
59 to the four LVDS multiplexer inputs.
62 display-timings are used instead.
64 Optional properties (required if display-timings are used):
65 - ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
66 - display-timings : A node that describes the display timings as defined in
67 Documentation/devicetree/bindings/display/panel/display-timing.txt.
68 - fsl,data-mapping : should be "spwg" or "jeida"
70 serialized LVDS signal.
71 - fsl,data-width : should be <18> or <24>
75 gpr: iomuxc-gpr@53fa8000 {
80 #address-cells = <1>;
81 #size-cells = <0>;
82 compatible = "fsl,imx53-ldb";
90 clock-names = "di0_pll", "di1_pll",
94 /* Using an of-graph endpoint link to connect the panel */
95 lvds-channel@0 {
96 #address-cells = <1>;
97 #size-cells = <0>;
104 remote-endpoint = <&ipu_di0_lvds0>;
112 remote-endpoint = <&panel_in>;
117 /* Using display-timings and fsl,data-mapping/width instead */
118 lvds-channel@1 {
119 #address-cells = <1>;
120 #size-cells = <0>;
122 fsl,data-mapping = "spwg";
123 fsl,data-width = <24>;
125 display-timings {
133 remote-endpoint = <&ipu_di1_lvds1>;
139 panel: lvds-panel {
144 remote-endpoint = <&lvds0_out>;