Lines Matching +full:dsi +full:- +full:controller
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/samsung,mipi-dsim.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung MIPI DSIM bridge controller
10 - Inki Dae <inki.dae@samsung.com>
11 - Jagan Teki <jagan@amarulasolutions.com>
12 - Marek Szyprowski <m.szyprowski@samsung.com>
15 Samsung MIPI DSIM bridge controller can be found it on Exynos
21 - enum:
22 - samsung,exynos3250-mipi-dsi
23 - samsung,exynos4210-mipi-dsi
24 - samsung,exynos5410-mipi-dsi
25 - samsung,exynos5422-mipi-dsi
26 - samsung,exynos5433-mipi-dsi
27 - fsl,imx8mm-mipi-dsim
28 - fsl,imx8mp-mipi-dsim
29 - items:
30 - const: fsl,imx8mn-mipi-dsim
31 - const: fsl,imx8mm-mipi-dsim
39 '#address-cells':
42 '#size-cells':
49 clock-names:
53 samsung,phy-type:
55 description: phandle to the samsung phy-type
57 power-domains:
60 samsung,power-domain:
64 vddcore-supply:
67 vddio-supply:
70 samsung,burst-clock-frequency:
77 samsung,esc-clock-frequency:
82 samsung,pll-clock-frequency:
91 phy-names:
102 display controller. Exactly one endpoint must be
106 $ref: /schemas/graph.yaml#/$defs/port-base
109 DSI output port node to the panel or the next bridge
114 $ref: /schemas/media/video-interfaces.yaml#
118 data-lanes:
125 lane-polarities:
129 The Samsung MIPI DSI IP requires that all the data lanes have
133 lane-polarities: [data-lanes]
136 - clock-names
137 - clocks
138 - compatible
139 - interrupts
140 - reg
141 - samsung,esc-clock-frequency
144 - $ref: ../dsi-controller.yaml#
145 - if:
149 const: samsung,exynos5433-mipi-dsi
156 clock-names:
158 - const: bus_clk
159 - const: phyclk_mipidphy0_bitclkdiv8
160 - const: phyclk_mipidphy0_rxclkesc0
161 - const: sclk_rgb_vclk_to_dsim0
162 - const: sclk_mipi
166 - port@0
169 - ports
170 - vddcore-supply
171 - vddio-supply
173 - if:
177 const: samsung,exynos5410-mipi-dsi
184 clock-names:
186 - const: bus_clk
187 - const: pll_clk
190 - vddcore-supply
191 - vddio-supply
193 - if:
197 const: samsung,exynos4210-mipi-dsi
204 clock-names:
206 - const: bus_clk
207 - const: sclk_mipi
210 - vddcore-supply
211 - vddio-supply
213 - if:
217 const: samsung,exynos3250-mipi-dsi
224 clock-names:
226 - const: bus_clk
227 - const: pll_clk
230 - vddcore-supply
231 - vddio-supply
232 - samsung,phy-type
238 - |
239 #include <dt-bindings/clock/exynos5433.h>
240 #include <dt-bindings/gpio/gpio.h>
241 #include <dt-bindings/interrupt-controller/arm-gic.h>
243 dsi@13900000 {
244 compatible = "samsung,exynos5433-mipi-dsi";
248 phy-names = "dsim";
254 clock-names = "bus_clk",
259 power-domains = <&pd_disp>;
260 vddcore-supply = <&ldo6_reg>;
261 vddio-supply = <&ldo7_reg>;
262 samsung,burst-clock-frequency = <512000000>;
263 samsung,esc-clock-frequency = <16000000>;
264 samsung,pll-clock-frequency = <24000000>;
265 pinctrl-names = "default";
266 pinctrl-0 = <&te_irq>;
269 #address-cells = <1>;
270 #size-cells = <0>;
276 remote-endpoint = <&mic_to_dsi>;