Lines Matching +full:qdu1000 +full:- +full:gcc
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/cpufreq/cpufreq-qcom-hw.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
21 - description: v1 of CPUFREQ HW
23 - enum:
24 - qcom,qcm2290-cpufreq-hw
25 - qcom,sc7180-cpufreq-hw
26 - qcom,sdm670-cpufreq-hw
27 - qcom,sdm845-cpufreq-hw
28 - qcom,sm6115-cpufreq-hw
29 - qcom,sm6350-cpufreq-hw
30 - qcom,sm8150-cpufreq-hw
31 - const: qcom,cpufreq-hw
33 - description: v2 of CPUFREQ HW (EPSS)
35 - enum:
36 - qcom,qdu1000-cpufreq-epss
37 - qcom,sa8775p-cpufreq-epss
38 - qcom,sc7280-cpufreq-epss
39 - qcom,sc8280xp-cpufreq-epss
40 - qcom,sdx75-cpufreq-epss
41 - qcom,sm4450-cpufreq-epss
42 - qcom,sm6375-cpufreq-epss
43 - qcom,sm8250-cpufreq-epss
44 - qcom,sm8350-cpufreq-epss
45 - qcom,sm8450-cpufreq-epss
46 - qcom,sm8550-cpufreq-epss
47 - qcom,sm8650-cpufreq-epss
48 - const: qcom,cpufreq-epss
53 - description: Frequency domain 0 register region
54 - description: Frequency domain 1 register region
55 - description: Frequency domain 2 register region
56 - description: Frequency domain 3 register region
58 reg-names:
61 - const: freq-domain0
62 - const: freq-domain1
63 - const: freq-domain2
64 - const: freq-domain3
68 - description: XO Clock
69 - description: GPLL0 Clock
71 clock-names:
73 - const: xo
74 - const: alternate
80 interrupt-names:
83 - const: dcvsh-irq-0
84 - const: dcvsh-irq-1
85 - const: dcvsh-irq-2
86 - const: dcvsh-irq-3
88 '#freq-domain-cells':
91 '#clock-cells':
95 - compatible
96 - reg
97 - clocks
98 - clock-names
99 - '#freq-domain-cells'
104 - if:
109 - qcom,qcm2290-cpufreq-hw
116 reg-names:
124 interrupt-names:
127 - if:
132 - qcom,qdu1000-cpufreq-epss
133 - qcom,sc7180-cpufreq-hw
134 - qcom,sc8280xp-cpufreq-epss
135 - qcom,sdm670-cpufreq-hw
136 - qcom,sdm845-cpufreq-hw
137 - qcom,sm4450-cpufreq-epss
138 - qcom,sm6115-cpufreq-hw
139 - qcom,sm6350-cpufreq-hw
140 - qcom,sm6375-cpufreq-epss
147 reg-names:
155 interrupt-names:
158 - if:
163 - qcom,sc7280-cpufreq-epss
164 - qcom,sm8250-cpufreq-epss
165 - qcom,sm8350-cpufreq-epss
166 - qcom,sm8450-cpufreq-epss
167 - qcom,sm8550-cpufreq-epss
174 reg-names:
182 interrupt-names:
185 - if:
190 - qcom,sm8150-cpufreq-hw
197 reg-names:
206 interrupt-names:
211 - |
212 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
213 #include <dt-bindings/clock/qcom,rpmh.h>
215 // Example 1: Dual-cluster, Quad-core per cluster. CPUs within a cluster
218 #address-cells = <2>;
219 #size-cells = <0>;
225 enable-method = "psci";
226 next-level-cache = <&L2_0>;
227 qcom,freq-domain = <&cpufreq_hw 0>;
229 L2_0: l2-cache {
231 cache-unified;
232 cache-level = <2>;
233 next-level-cache = <&L3_0>;
234 L3_0: l3-cache {
236 cache-unified;
237 cache-level = <3>;
246 enable-method = "psci";
247 next-level-cache = <&L2_100>;
248 qcom,freq-domain = <&cpufreq_hw 0>;
250 L2_100: l2-cache {
252 cache-unified;
253 cache-level = <2>;
254 next-level-cache = <&L3_0>;
262 enable-method = "psci";
263 next-level-cache = <&L2_200>;
264 qcom,freq-domain = <&cpufreq_hw 0>;
266 L2_200: l2-cache {
268 cache-unified;
269 cache-level = <2>;
270 next-level-cache = <&L3_0>;
278 enable-method = "psci";
279 next-level-cache = <&L2_300>;
280 qcom,freq-domain = <&cpufreq_hw 0>;
282 L2_300: l2-cache {
284 cache-unified;
285 cache-level = <2>;
286 next-level-cache = <&L3_0>;
294 enable-method = "psci";
295 next-level-cache = <&L2_400>;
296 qcom,freq-domain = <&cpufreq_hw 1>;
298 L2_400: l2-cache {
300 cache-unified;
301 cache-level = <2>;
302 next-level-cache = <&L3_0>;
310 enable-method = "psci";
311 next-level-cache = <&L2_500>;
312 qcom,freq-domain = <&cpufreq_hw 1>;
314 L2_500: l2-cache {
316 cache-unified;
317 cache-level = <2>;
318 next-level-cache = <&L3_0>;
326 enable-method = "psci";
327 next-level-cache = <&L2_600>;
328 qcom,freq-domain = <&cpufreq_hw 1>;
330 L2_600: l2-cache {
332 cache-unified;
333 cache-level = <2>;
334 next-level-cache = <&L3_0>;
342 enable-method = "psci";
343 next-level-cache = <&L2_700>;
344 qcom,freq-domain = <&cpufreq_hw 1>;
346 L2_700: l2-cache {
348 cache-unified;
349 cache-level = <2>;
350 next-level-cache = <&L3_0>;
356 #address-cells = <1>;
357 #size-cells = <1>;
360 compatible = "qcom,sdm845-cpufreq-hw", "qcom,cpufreq-hw";
362 reg-names = "freq-domain0", "freq-domain1";
364 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
365 clock-names = "xo", "alternate";
367 #freq-domain-cells = <1>;
368 #clock-cells = <1>;