Lines Matching +full:idle +full:- +full:state +full:- +full:spc
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/cpu/idle-states.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Idle states
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
11 - Anup Patel <anup@brainfault.org>
15 1 - Introduction
18 ARM and RISC-V systems contain HW capable of managing power consumption
19 dynamically, where cores can be put in different low-power states (ranging
21 representing the range of dynamic idle states that a processor can enter at
22 run-time, can be specified through device tree bindings representing the
23 parameters required to enter/exit specific idle states on a given processor.
26 2 - ARM idle states
32 - Running
33 - Idle_standby
34 - Idle_retention
35 - Sleep
36 - Off
40 PM implementation to put the processor in different idle states (which include
41 states listed above; "off" state is not an idle state since it does not have
42 wake-up capabilities, hence it is not considered in this document).
44 Idle state parameters (e.g. entry latency) are platform specific and need to
48 The device tree binding definition for ARM idle states is the subject of this
52 3 - RISC-V idle states
55 On RISC-V systems, the HARTs (or CPUs) [6] can be put in platform specific
56 suspend (or idle) states (ranging from simple WFI, power gating, etc). The
57 RISC-V SBI v0.3 (or higher) [7] hart state management extension provides a
58 standard mechanism for OS to request HART state transitions.
60 The platform specific suspend (or idle) states of a hart can be either
61 retentive or non-rententive in nature. A retentive suspend state will
63 a non-retentive suspend state will not preserve HART registers and CSR
67 4 - idle-states definitions
70 Idle states are characterized for a specific system through a set of
72 triggered upon idle states entry and exit.
75 properties required to enter and exit an idle state:
77 ..__[EXEC]__|__[PREP]__|__[ENTRY]__|__[IDLE]__|__[EXIT]__|__[EXEC]__..
80 |<------ entry ------->|
82 |<- exit ->|
84 |<-------- min-residency -------->|
85 |<------- wakeup-latency ------->|
87 Diagram 1: CPU idle state execution phases
91 PREP: Preparation phase before committing the hardware to idle mode
92 like cache flushing. This is abortable on pending wake-up
98 ENTRY: The hardware is committed to idle mode. This period must run
99 to completion up to IDLE before anything else can happen.
101 IDLE: This is the actual energy-saving idle period. This may last
102 between 0 and infinite time, until a wake-up event occurs.
107 entry-latency: Worst case latency required to enter the idle state. The
108 exit-latency may be guaranteed only after entry-latency has passed.
110 min-residency: Minimum period, including preparation and entry, for a given
111 idle state to be worthwhile energywise.
113 wakeup-latency: Maximum delay between the signaling of a wake-up event and the
115 to be entry-latency + exit-latency.
119 An idle CPU requires the expected min-residency time to select the most
120 appropriate idle state based on the expected expiry time of the next IRQ
121 (i.e. wake-up) that causes the CPU to return to the EXEC phase.
123 An operating system scheduler may need to compute the shortest wake-up delay
125 of an idle state, e.g.:
127 wakeup-delay = exit-latency + max(entry-latency - (now - entry-timestamp), 0)
130 (e.g. waking-up) the CPU with the shortest wake-up delay.
131 The wake-up delay must take into account the entry latency if that period
135 state).
137 An OS has to reliably probe the wakeup-latency since some devices can enforce
139 worst case wake-up latency it can incur if a CPU is allowed to enter an
140 idle state, and possibly to prevent that to guarantee reliable device
143 The min-residency time parameter deserves further explanation since it is
146 The energy consumption of a cpu when it enters a power state can be roughly
153 n | /---
154 e | /------
155 r | /------
156 g | /-----
157 y | /------
158 | ----
166 -----|-------+----------------------------------
171 The graph is split in two parts delimited by time 1ms on the X-axis.
172 The graph curve with X-axis values = { x | 0 < x < 1ms } has a steep slope
173 and denotes the energy costs incurred while entering and leaving the idle
174 state.
175 The graph curve in the area delimited by X-axis values = {x | x > 1ms } has
176 shallower slope and essentially represents the energy consumption of the idle
177 state.
179 min-residency is defined for a given idle state as the minimum expected
180 residency time for a state (inclusive of preparation and entry) after
181 which choosing that state become the most energy efficient option. A good
185 For sake of simplicity, let's consider a system with two idle states IDLE1,
191 | /-- IDLE1
192 e | /---
193 n | /----
194 e | /---
195 r | /-----/--------- IDLE2
196 g | /-------/---------
197 y | ------------ /---|
198 | / /---- |
199 | / /--- |
200 | / /---- |
201 | / /--- |
202 | --- |
206 ---/----------------------------+------------------------
207 |IDLE1-energy < IDLE2-energy | IDLE2-energy < IDLE1-energy
209 IDLE2-min-residency
211 Graph 2: idle states min-residency example
213 In graph 2 above, that takes into account idle states entry/exit energy
214 costs, it is clear that if the idle state residency time (i.e. time till next
215 wake-up IRQ) is less than IDLE2-min-residency, IDLE1 is the better idle state
222 idle state IDLE2 implies that after a suitable time, IDLE2 becomes more energy
226 shallower states in a system with multiple idle states) is defined
227 IDLE2-min-residency and corresponds to the time when energy consumption of
230 The definitions provided in this section underpin the idle states
234 5 - idle-states node
237 The processor idle states are defined within the idle-states node, which is
239 processor idle states, defined as device tree nodes, are listed.
241 On ARM systems, it is a container of processor idle states nodes. If the
243 just supports idle_standby, an idle-states node is not required.
246 6 - Qualcomm specific STATES
249 Idle states have different enter/exit latency and residency values.
250 The idle states supported by the QCOM SoC are defined as -
254 * Standalone Power Collapse (Standalone PC or SPC)
260 trigger to execute the SPM state machine. The SPM state machine waits for the
262 hierarchy to enter standby states, when all cpus are idle. An interrupt brings
263 the SPM state machine out of its wait, the next step is to ensure that the
265 execution. This state is defined as a generic ARM WFI state by the ARM cpuidle
266 driver and is not defined in the DT. The SPM state machine should be
267 configured to execute this state by default and after executing every other
268 state below.
270 Retention: Retention is a low power state where the core is clock gated and
275 state. Retention may have a slightly higher latency than Standby.
278 between the time it enters idle and the next known wake up. SPC mode is used
279 to indicate a core entering a power down state without consulting any other
281 sequence for this idle state is programmed to power down the supply to the
283 system state including cache hierarchy is ready before allowing core to
286 kernel. Entering a power down state for the cpu, needs to be done by trapping
288 code in the EL for the SoC. On SoCs with write-back L1 cache, the cache has to
291 Power Collapse: This state is similar to the SPC mode, but distinguishes
294 be flushed, system bus, clocks - lowered, and SoC main XO clock gated and
295 voltages reduced, provided all cpus enter this state. Since the span of low
296 power modes possible at this state is vast, the exit latency and the residency
298 this essentially is cpu power down. The SPM in this state also may handshake
303 7 - References
306 [1] ARM Linux Kernel documentation - CPUs bindings
309 [2] ARM Linux Kernel documentation - PSCI bindings
318 [5] ARM Linux Kernel documentation - Booting AArch64 Linux
321 [6] RISC-V Linux Kernel documentation - CPUs bindings
324 [7] RISC-V Supervisor Binary Interface (SBI)
325 http://github.com/riscv/riscv-sbi-doc/riscv-sbi.adoc
329 const: idle-states
331 entry-method:
335 On ARM v8 64-bit this property is required.
336 On ARM 32-bit systems this property is optional
338 This assumes that the "enable-method" property is set to "psci" in the cpu
339 node[5] that is responsible for setting up CPU idle management in the OS
344 "^(cpu|cluster)-":
347 Each state node represents an idle state description and must be defined
350 The idle state entered by executing the wfi instruction (idle_standby
351 SBSA,[3][4]) is considered standard on all ARM and RISC-V platforms and
354 In addition to the properties listed above, a state node may require
355 additional properties specific to the entry-method defined in the
356 idle-states node. Please refer to the entry-method bindings
362 - items:
363 - enum:
364 - qcom,idle-state-ret
365 - qcom,idle-state-spc
366 - qcom,idle-state-pc
367 - const: arm,idle-state
368 - enum:
369 - arm,idle-state
370 - riscv,idle-state
372 arm,psci-suspend-param:
378 (i.e. idle states node with entry-method property is set to "psci")
381 riscv,sbi-suspend-param:
384 suspend_type parameter to pass to the RISC-V SBI HSM suspend call.
386 This property is required in idle state nodes of device tree meant
387 for RISC-V systems. For more details on the suspend_type parameter
390 local-timer-stop:
393 lost on state entry, otherwise it is retained.
396 entry-latency-us:
398 Worst case latency in microseconds required to enter the idle state.
400 exit-latency-us:
402 Worst case latency in microseconds required to exit the idle state.
403 The exit-latency-us duration may be guaranteed only after
404 entry-latency-us has passed.
406 min-residency-us:
409 and entry, for this idle state to be considered worthwhile energy wise
412 wakeup-latency-us:
414 Maximum delay between the signaling of a wake-up event and the CPU
418 entry-latency-us + exit-latency-us
421 PREP phase (see diagram 1, section 2) is non-neglibigle. In such
422 systems entry-latency-us + exit-latency-us will exceed
423 wakeup-latency-us by this duration.
425 idle-state-name:
428 A string used as a descriptive name for the idle state.
433 - compatible
434 - entry-latency-us
435 - exit-latency-us
436 - min-residency-us
441 - |
444 #size-cells = <0>;
445 #address-cells = <2>;
449 compatible = "arm,cortex-a57";
451 enable-method = "psci";
452 cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
458 compatible = "arm,cortex-a57";
460 enable-method = "psci";
461 cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
467 compatible = "arm,cortex-a57";
469 enable-method = "psci";
470 cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
476 compatible = "arm,cortex-a57";
478 enable-method = "psci";
479 cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
485 compatible = "arm,cortex-a57";
487 enable-method = "psci";
488 cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
494 compatible = "arm,cortex-a57";
496 enable-method = "psci";
497 cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
503 compatible = "arm,cortex-a57";
505 enable-method = "psci";
506 cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
512 compatible = "arm,cortex-a57";
514 enable-method = "psci";
515 cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
521 compatible = "arm,cortex-a53";
523 enable-method = "psci";
524 cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
530 compatible = "arm,cortex-a53";
532 enable-method = "psci";
533 cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
539 compatible = "arm,cortex-a53";
541 enable-method = "psci";
542 cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
548 compatible = "arm,cortex-a53";
550 enable-method = "psci";
551 cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
557 compatible = "arm,cortex-a53";
559 enable-method = "psci";
560 cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
566 compatible = "arm,cortex-a53";
568 enable-method = "psci";
569 cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
575 compatible = "arm,cortex-a53";
577 enable-method = "psci";
578 cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
584 compatible = "arm,cortex-a53";
586 enable-method = "psci";
587 cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
591 idle-states {
592 entry-method = "psci";
594 CPU_RETENTION_0_0: cpu-retention-0-0 {
595 compatible = "arm,idle-state";
596 arm,psci-suspend-param = <0x0010000>;
597 entry-latency-us = <20>;
598 exit-latency-us = <40>;
599 min-residency-us = <80>;
602 CLUSTER_RETENTION_0: cluster-retention-0 {
603 compatible = "arm,idle-state";
604 local-timer-stop;
605 arm,psci-suspend-param = <0x1010000>;
606 entry-latency-us = <50>;
607 exit-latency-us = <100>;
608 min-residency-us = <250>;
609 wakeup-latency-us = <130>;
612 CPU_SLEEP_0_0: cpu-sleep-0-0 {
613 compatible = "arm,idle-state";
614 local-timer-stop;
615 arm,psci-suspend-param = <0x0010000>;
616 entry-latency-us = <250>;
617 exit-latency-us = <500>;
618 min-residency-us = <950>;
621 CLUSTER_SLEEP_0: cluster-sleep-0 {
622 compatible = "arm,idle-state";
623 local-timer-stop;
624 arm,psci-suspend-param = <0x1010000>;
625 entry-latency-us = <600>;
626 exit-latency-us = <1100>;
627 min-residency-us = <2700>;
628 wakeup-latency-us = <1500>;
631 CPU_RETENTION_1_0: cpu-retention-1-0 {
632 compatible = "arm,idle-state";
633 arm,psci-suspend-param = <0x0010000>;
634 entry-latency-us = <20>;
635 exit-latency-us = <40>;
636 min-residency-us = <90>;
639 CLUSTER_RETENTION_1: cluster-retention-1 {
640 compatible = "arm,idle-state";
641 local-timer-stop;
642 arm,psci-suspend-param = <0x1010000>;
643 entry-latency-us = <50>;
644 exit-latency-us = <100>;
645 min-residency-us = <270>;
646 wakeup-latency-us = <100>;
649 CPU_SLEEP_1_0: cpu-sleep-1-0 {
650 compatible = "arm,idle-state";
651 local-timer-stop;
652 arm,psci-suspend-param = <0x0010000>;
653 entry-latency-us = <70>;
654 exit-latency-us = <100>;
655 min-residency-us = <300>;
656 wakeup-latency-us = <150>;
659 CLUSTER_SLEEP_1: cluster-sleep-1 {
660 compatible = "arm,idle-state";
661 local-timer-stop;
662 arm,psci-suspend-param = <0x1010000>;
663 entry-latency-us = <500>;
664 exit-latency-us = <1200>;
665 min-residency-us = <3500>;
666 wakeup-latency-us = <1300>;
671 - |
672 // Example 2 (ARM 32-bit, 8-cpu system, two clusters):
675 #size-cells = <0>;
676 #address-cells = <1>;
680 compatible = "arm,cortex-a15";
682 cpu-idle-states = <&cpu_sleep_0_0>, <&cluster_sleep_0>;
687 compatible = "arm,cortex-a15";
689 cpu-idle-states = <&cpu_sleep_0_0>, <&cluster_sleep_0>;
694 compatible = "arm,cortex-a15";
696 cpu-idle-states = <&cpu_sleep_0_0>, <&cluster_sleep_0>;
701 compatible = "arm,cortex-a15";
703 cpu-idle-states = <&cpu_sleep_0_0>, <&cluster_sleep_0>;
708 compatible = "arm,cortex-a7";
710 cpu-idle-states = <&cpu_sleep_1_0>, <&cluster_sleep_1>;
715 compatible = "arm,cortex-a7";
717 cpu-idle-states = <&cpu_sleep_1_0>, <&cluster_sleep_1>;
722 compatible = "arm,cortex-a7";
724 cpu-idle-states = <&cpu_sleep_1_0>, <&cluster_sleep_1>;
729 compatible = "arm,cortex-a7";
731 cpu-idle-states = <&cpu_sleep_1_0>, <&cluster_sleep_1>;
734 idle-states {
735 cpu_sleep_0_0: cpu-sleep-0-0 {
736 compatible = "arm,idle-state";
737 local-timer-stop;
738 entry-latency-us = <200>;
739 exit-latency-us = <100>;
740 min-residency-us = <400>;
741 wakeup-latency-us = <250>;
744 cluster_sleep_0: cluster-sleep-0 {
745 compatible = "arm,idle-state";
746 local-timer-stop;
747 entry-latency-us = <500>;
748 exit-latency-us = <1500>;
749 min-residency-us = <2500>;
750 wakeup-latency-us = <1700>;
753 cpu_sleep_1_0: cpu-sleep-1-0 {
754 compatible = "arm,idle-state";
755 local-timer-stop;
756 entry-latency-us = <300>;
757 exit-latency-us = <500>;
758 min-residency-us = <900>;
759 wakeup-latency-us = <600>;
762 cluster_sleep_1: cluster-sleep-1 {
763 compatible = "arm,idle-state";
764 local-timer-stop;
765 entry-latency-us = <800>;
766 exit-latency-us = <2000>;
767 min-residency-us = <6500>;
768 wakeup-latency-us = <2300>;
773 - |
774 // Example 3 (RISC-V 64-bit, 4-cpu systems, two clusters):
777 #size-cells = <0>;
778 #address-cells = <1>;
785 mmu-type = "riscv,sv48";
786 cpu-idle-states = <&CPU_RET_0_0>, <&CPU_NONRET_0_0>,
789 cpu_intc0: interrupt-controller {
790 #interrupt-cells = <1>;
791 compatible = "riscv,cpu-intc";
792 interrupt-controller;
801 mmu-type = "riscv,sv48";
802 cpu-idle-states = <&CPU_RET_0_0>, <&CPU_NONRET_0_0>,
805 cpu_intc1: interrupt-controller {
806 #interrupt-cells = <1>;
807 compatible = "riscv,cpu-intc";
808 interrupt-controller;
817 mmu-type = "riscv,sv48";
818 cpu-idle-states = <&CPU_RET_1_0>, <&CPU_NONRET_1_0>,
821 cpu_intc10: interrupt-controller {
822 #interrupt-cells = <1>;
823 compatible = "riscv,cpu-intc";
824 interrupt-controller;
833 mmu-type = "riscv,sv48";
834 cpu-idle-states = <&CPU_RET_1_0>, <&CPU_NONRET_1_0>,
837 cpu_intc11: interrupt-controller {
838 #interrupt-cells = <1>;
839 compatible = "riscv,cpu-intc";
840 interrupt-controller;
844 idle-states {
845 CPU_RET_0_0: cpu-retentive-0-0 {
846 compatible = "riscv,idle-state";
847 riscv,sbi-suspend-param = <0x10000000>;
848 entry-latency-us = <20>;
849 exit-latency-us = <40>;
850 min-residency-us = <80>;
853 CPU_NONRET_0_0: cpu-nonretentive-0-0 {
854 compatible = "riscv,idle-state";
855 riscv,sbi-suspend-param = <0x90000000>;
856 entry-latency-us = <250>;
857 exit-latency-us = <500>;
858 min-residency-us = <950>;
861 CLUSTER_RET_0: cluster-retentive-0 {
862 compatible = "riscv,idle-state";
863 riscv,sbi-suspend-param = <0x11000000>;
864 local-timer-stop;
865 entry-latency-us = <50>;
866 exit-latency-us = <100>;
867 min-residency-us = <250>;
868 wakeup-latency-us = <130>;
871 CLUSTER_NONRET_0: cluster-nonretentive-0 {
872 compatible = "riscv,idle-state";
873 riscv,sbi-suspend-param = <0x91000000>;
874 local-timer-stop;
875 entry-latency-us = <600>;
876 exit-latency-us = <1100>;
877 min-residency-us = <2700>;
878 wakeup-latency-us = <1500>;
881 CPU_RET_1_0: cpu-retentive-1-0 {
882 compatible = "riscv,idle-state";
883 riscv,sbi-suspend-param = <0x10000010>;
884 entry-latency-us = <20>;
885 exit-latency-us = <40>;
886 min-residency-us = <80>;
889 CPU_NONRET_1_0: cpu-nonretentive-1-0 {
890 compatible = "riscv,idle-state";
891 riscv,sbi-suspend-param = <0x90000010>;
892 entry-latency-us = <250>;
893 exit-latency-us = <500>;
894 min-residency-us = <950>;
897 CLUSTER_RET_1: cluster-retentive-1 {
898 compatible = "riscv,idle-state";
899 riscv,sbi-suspend-param = <0x11000010>;
900 local-timer-stop;
901 entry-latency-us = <50>;
902 exit-latency-us = <100>;
903 min-residency-us = <250>;
904 wakeup-latency-us = <130>;
907 CLUSTER_NONRET_1: cluster-nonretentive-1 {
908 compatible = "riscv,idle-state";
909 riscv,sbi-suspend-param = <0x91000010>;
910 local-timer-stop;
911 entry-latency-us = <600>;
912 exit-latency-us = <1100>;
913 min-residency-us = <2700>;
914 wakeup-latency-us = <1500>;
919 // Example 4 - Qualcomm SPC
920 idle-states {
921 cpu_spc: cpu-spc {
922 compatible = "qcom,idle-state-spc", "arm,idle-state";
923 entry-latency-us = <150>;
924 exit-latency-us = <200>;
925 min-residency-us = <2000>;