Lines Matching +full:dsp +full:- +full:reset

3 The PSC provides power management, clock gating and reset functionality. It is
7 - compatible: shall be one of:
8 	- "ti,da850-psc0" for PSC0 on DA850/OMAP-L138/AM18XX
9 	- "ti,da850-psc1" for PSC1 on DA850/OMAP-L138/AM18XX
10 - reg: physical base address and size of the controller's register area
11 - #clock-cells: from common clock binding; shall be set to 1
12 - #power-domain-cells: from generic power domain binding; shall be set to 1.
13 - clocks: phandles to clocks corresponding to the clock-names property
14 - clock-names: list of parent clock names - depends on compatible value
15 	- for "ti,da850-psc0", shall be "pll0_sysclk1", "pll0_sysclk2",
17 	- for "ti,da850-psc1", shall be "pll0_sysclk2", "pll0_sysclk4", "async3"
20 - #reset-cells: from reset binding; shall be set to 1 - only applicable when
21   at least one local domain provides a local reset.
25 	Clock, power domain and reset consumers shall use the local power domain
27 	the device-specific datasheet to find these numbers. NB: Most local
28 	domains	only provide a clock/power domain and not a reset.
32 	psc0: clock-controller@10000 {
33 		compatible = "ti,da850-psc0";
35 		#clock-cells = <1>;
36 		#power-domain-cells = <1>;
37 		#reset-cells = <1>;
43 	psc1: clock-controller@227000 {
44 		compatible = "ti,da850-psc1";
46 		#clock-cells = <1>;
47 		#power-domain-cells = <1>;
53 	dsp: dsp@11800000 {
54 		compatible = "ti,da850-dsp";
60 		reg-names = "l2sram", "l1pram", "l1dram", "host1cfg", "chipsig";
61 		interrupt-parent = <&intc>;
64 		power-domains = <&psc0 15>;
69 - Documentation/devicetree/bindings/clock/clock-bindings.txt
70 - Documentation/devicetree/bindings/power/power-domain.yaml
71 - Documentation/devicetree/bindings/reset/reset.txt