Lines Matching +full:clkout +full:- +full:clock

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/stericsson,u8500-clks.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsson DB8500 (U8500) clocks
10   - Ulf Hansson <ulf.hansson@linaro.org>
11   - Linus Walleij <linus.walleij@linaro.org>
14   DB8500 digital baseband system-on-chip and its siblings such as
16   itself, not off-chip clocks. There are four different on-chip
17   clocks - RTC (32 kHz), CPU clock (SMP TWD), PRCMU (power reset and
19   clock controller) clocks. For some reason PRCC 4 does not exist so
25       - stericsson,u8500-clks
26       - stericsson,u8540-clks
27       - stericsson,u9540-clks
31       - description: PRCC 1 register area
32       - description: PRCC 2 register area
33       - description: PRCC 3 register area
34       - description: PRCC 5 register area
35       - description: PRCC 6 register area
37   prcmu-clock:
38     description: A subnode with one clock cell for PRCMU (power, reset, control
39       management unit) clocks. The cell indicates which PRCMU clock in the
40       prcmu-clock node the consumer wants to use.
44       '#clock-cells':
49   prcc-periph-clock:
50     description: A subnode with two clock cells for PRCC (peripheral
51       reset and clock controller) peripheral clocks. The first cell indicates
53       5, 6. The second cell indicates which clock inside the PRCC block it
58       '#clock-cells':
63   prcc-kernel-clock:
64     description: A subnode with two clock cells for PRCC (peripheral reset
65       and clock controller) kernel clocks. The first cell indicates which PRCC
67       second cell indicates which clock inside the PRCC block it wants, possible
72       '#clock-cells':
77   prcc-reset-controller:
79       PRCC (peripheral reset and clock controller). The first cell indicates
86       '#reset-cells':
91   rtc32k-clock:
92     description: A subnode with zero clock cells for the 32kHz RTC clock.
96       '#clock-cells':
101   smp-twd-clock:
103       clock cells.
107       '#clock-cells':
112   clkout-clock:
113     description: A subnode with three clock cells for externally routed clocks,
114       output clocks. These are two PRCMU-internal clocks that can be divided and
119       '#clock-cells':
121           The first cell indicates which output clock we are using,
123           The second cell indicates which clock we want to use as source,
132   - compatible
133   - reg
134   - prcmu-clock
135   - prcc-periph-clock
136   - prcc-kernel-clock
137   - rtc32k-clock
138   - smp-twd-clock
143   - |
144     #include <dt-bindings/clock/ste-db8500-clkout.h>
146       compatible = "stericsson,u8500-clks";
151       prcmu_clk: prcmu-clock {
152         #clock-cells = <1>;
155       prcc_pclk: prcc-periph-clock {
156         #clock-cells = <2>;
159       prcc_kclk: prcc-kernel-clock {
160         #clock-cells = <2>;
163       prcc_reset: prcc-reset-controller {
164         #reset-cells = <2>;
167       rtc_clk: rtc32k-clock {
168         #clock-cells = <0>;
171       smp_twd_clk: smp-twd-clock {
172         #clock-cells = <0>;
175       clkout_clk: clkout-clock {
176         #clock-cells = <3>;