Lines Matching +full:fu540 +full:- +full:c000 +full:- +full:prci

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/sifive/fu540-prci.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive FU540 Power Reset Clock Interrupt Controller (PRCI)
11   - Paul Walmsley  <paul.walmsley@sifive.com>
14   On the FU540 family of SoCs, most system-wide clock and reset integration
15   is via the PRCI IP block.
17   macros defined in include/dt-bindings/clock/sifive-fu540-prci.h.
26     const: sifive,fu540-c000-prci
33       - description: high frequency clock.
34       - description: RTL clock.
36   clock-names:
38       - const: hfclk
39       - const: rtcclk
41   "#clock-cells":
45   - compatible
46   - reg
47   - clocks
48   - "#clock-cells"
53   - |
54     prci: clock-controller@10000000 {
55       compatible = "sifive,fu540-c000-prci";
58       #clock-cells = <1>;