Lines Matching +full:index +full:- +full:power +full:- +full:of +full:- +full:two
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
14 and control of clock signals for the IP modules, generation and control of resets,
15 and control over booting, low power consumption and power supply domains.
19 const: renesas,r9a09g057-cpg
26 - description: AUDIO_EXTAL clock input
27 - description: RTXIN clock input
28 - description: QEXTAL clock input
30 clock-names:
32 - const: audio_extal
33 - const: rtxin
34 - const: qextal
36 '#clock-cells':
38 - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"
40 <dt-bindings/clock/renesas,r9a09g057-cpg.h>,
41 - For module clocks, the two clock specifier cells must be "CPG_MOD" and
43 offset index multiplied by 16, plus the actual bit in the register
48 '#power-domain-cells':
51 '#reset-cells':
54 is calculated as the reset register offset index multiplied by 16, plus the
60 - compatible
61 - reg
62 - clocks
63 - clock-names
64 - '#clock-cells'
65 - '#power-domain-cells'
66 - '#reset-cells'
71 - |
72 clock-controller@10420000 {
73 compatible = "renesas,r9a09g057-cpg";
76 clock-names = "audio_extal", "rtxin", "qextal";
77 #clock-cells = <2>;
78 #power-domain-cells = <0>;
79 #reset-cells = <1>;