Lines Matching +full:sm8550 +full:- +full:gcc

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sm8550-dispcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display Clock & Reset Controller for SM8550
10   - Bjorn Andersson <andersson@kernel.org>
11   - Neil Armstrong <neil.armstrong@linaro.org>
15   domains on SM8550.
18   - include/dt-bindings/clock/qcom,sm8550-dispcc.h
19   - include/dt-bindings/clock/qcom,sm8650-dispcc.h
20   - include/dt-bindings/clock/qcom,x1e80100-dispcc.h
25       - qcom,sm8550-dispcc
26       - qcom,sm8650-dispcc
27       - qcom,x1e80100-dispcc
31       - description: Board XO source
32       - description: Board Always On XO source
33       - description: Display's AHB clock
34       - description: sleep clock
35       - description: Byte clock from DSI PHY0
36       - description: Pixel clock from DSI PHY0
37       - description: Byte clock from DSI PHY1
38       - description: Pixel clock from DSI PHY1
39       - description: Link clock from DP PHY0
40       - description: VCO DIV clock from DP PHY0
41       - description: Link clock from DP PHY1
42       - description: VCO DIV clock from DP PHY1
43       - description: Link clock from DP PHY2
44       - description: VCO DIV clock from DP PHY2
45       - description: Link clock from DP PHY3
46       - description: VCO DIV clock from DP PHY3
48   power-domains:
53   required-opps:
59   - compatible
60   - clocks
61   - '#power-domain-cells'
64   - $ref: qcom,gcc.yaml#
69   - |
70     #include <dt-bindings/clock/qcom,sm8550-gcc.h>
71     #include <dt-bindings/clock/qcom,rpmh.h>
72     #include <dt-bindings/power/qcom,rpmhpd.h>
73     clock-controller@af00000 {
74       compatible = "qcom,sm8550-dispcc";
78                <&gcc GCC_DISP_AHB_CLK>,
92       #clock-cells = <1>;
93       #reset-cells = <1>;
94       #power-domain-cells = <1>;
95       power-domains = <&rpmhpd RPMHPD_MMCX>;
96       required-opps = <&rpmhpd_opp_low_svs>;