Lines Matching +full:sm8450 +full:- +full:videocc
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sm8450-videocc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Video Clock & Reset Controller on SM8450
10 - Taniya Das <quic_tdas@quicinc.com>
11 - Jagadeesh Kona <quic_jkona@quicinc.com>
15 domains on SM8450.
18 include/dt-bindings/clock/qcom,sm8450-videocc.h
19 include/dt-bindings/clock/qcom,sm8650-videocc.h
24 - qcom,sm8450-videocc
25 - qcom,sm8550-videocc
26 - qcom,sm8650-videocc
30 - description: Board XO source
31 - description: Video AHB clock from GCC
33 power-domains:
38 required-opps:
44 - compatible
45 - clocks
46 - power-domains
47 - '#power-domain-cells'
50 - $ref: qcom,gcc.yaml#
51 - if:
56 - qcom,sm8450-videocc
57 - qcom,sm8550-videocc
60 - required-opps
65 - |
66 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
67 #include <dt-bindings/clock/qcom,rpmh.h>
68 #include <dt-bindings/power/qcom,rpmhpd.h>
69 videocc: clock-controller@aaf0000 {
70 compatible = "qcom,sm8450-videocc";
74 power-domains = <&rpmhpd RPMHPD_MMCX>;
75 required-opps = <&rpmhpd_opp_low_svs>;
76 #clock-cells = <1>;
77 #reset-cells = <1>;
78 #power-domain-cells = <1>;