Lines Matching +full:sm8650 +full:- +full:gpucc
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sm8450-gpucc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Konrad Dybcio <konradybcio@kernel.org>
17 include/dt-bindings/clock/qcom,sm4450-gpucc.h
18 include/dt-bindings/clock/qcom,sm8450-gpucc.h
19 include/dt-bindings/clock/qcom,sm8550-gpucc.h
20 include/dt-bindings/reset/qcom,sm8450-gpucc.h
21 include/dt-bindings/reset/qcom,sm8650-gpucc.h
22 include/dt-bindings/reset/qcom,x1e80100-gpucc.h
27 - qcom,sm4450-gpucc
28 - qcom,sm8450-gpucc
29 - qcom,sm8550-gpucc
30 - qcom,sm8650-gpucc
31 - qcom,x1e80100-gpucc
35 - description: Board XO source
36 - description: GPLL0 main branch source
37 - description: GPLL0 div branch source
40 - compatible
41 - clocks
42 - '#power-domain-cells'
45 - $ref: qcom,gcc.yaml#
50 - |
51 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
52 #include <dt-bindings/clock/qcom,rpmh.h>
55 #address-cells = <2>;
56 #size-cells = <2>;
58 clock-controller@3d90000 {
59 compatible = "qcom,sm8450-gpucc";
64 #clock-cells = <1>;
65 #reset-cells = <1>;
66 #power-domain-cells = <1>;