Lines Matching +full:ufs +full:- +full:phy
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-apq8084.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stephen Boyd <sboyd@kernel.org>
11 - Taniya Das <quic_tdas@quicinc.com>
18 include/dt-bindings/clock/qcom,gcc-apq8084.h
19 include/dt-bindings/reset/qcom,gcc-apq8084.h
22 - $ref: qcom,gcc.yaml#
26 const: qcom,gcc-apq8084
30 - description: XO source
31 - description: Sleep clock source
32 - description: UFS RX symbol 0 clock
33 - description: UFS RX symbol 1 clock
34 - description: UFS TX symbol 0 clock
35 - description: UFS TX symbol 1 clock
36 - description: SATA ASIC0 clock
37 - description: SATA RX clock
38 - description: PCIe PIPE clock
40 clock-names:
42 - const: xo
43 - const: sleep_clk
44 - const: ufs_rx_symbol_0_clk_src
45 - const: ufs_rx_symbol_1_clk_src
46 - const: ufs_tx_symbol_0_clk_src
47 - const: ufs_tx_symbol_1_clk_src
48 - const: sata_asic0_clk
49 - const: sata_rx_clk
50 - const: pcie_pipe
53 - compatible
54 - '#power-domain-cells'
59 - |
60 /* UFS PHY on APQ8084 is not supported (yet), so these bindings just serve an example */
61 clock-controller@fc400000 {
62 compatible = "qcom,gcc-apq8084";
64 #clock-cells = <1>;
65 #reset-cells = <1>;
66 #power-domain-cells = <1>;
77 clock-names = "xo",