Lines Matching +full:sm6350 +full:- +full:dispcc
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,dispcc-sm6350.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display Clock & Reset Controller on SM6350
10 - Konrad Dybcio <konradybcio@kernel.org>
14 domains on SM6350.
16 See also:: include/dt-bindings/clock/qcom,dispcc-sm6350.h
20 const: qcom,sm6350-dispcc
24 - description: Board XO source
25 - description: GPLL0 source from GCC
26 - description: Byte clock from DSI PHY
27 - description: Pixel clock from DSI PHY
28 - description: Link clock from DP PHY
29 - description: VCO DIV clock from DP PHY
31 clock-names:
33 - const: bi_tcxo
34 - const: gcc_disp_gpll0_clk
35 - const: dsi0_phy_pll_out_byteclk
36 - const: dsi0_phy_pll_out_dsiclk
37 - const: dp_phy_pll_link_clk
38 - const: dp_phy_pll_vco_div_clk
41 - compatible
42 - clocks
43 - clock-names
44 - '#power-domain-cells'
47 - $ref: qcom,gcc.yaml#
52 - |
53 #include <dt-bindings/clock/qcom,gcc-sm6350.h>
54 #include <dt-bindings/clock/qcom,rpmh.h>
55 clock-controller@af00000 {
56 compatible = "qcom,sm6350-dispcc";
64 clock-names = "bi_tcxo",
70 #clock-cells = <1>;
71 #reset-cells = <1>;
72 #power-domain-cells = <1>;