Lines Matching +full:mt8192 +full:- +full:imgsys
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/mediatek,mt8192-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek Functional Clock Controller for MT8192
10 - Chun-Jie Chen <chun-jie.chen@mediatek.com>
13 The Mediatek functional clock controller provides various clocks on MT8192.
18 - enum:
19 - mediatek,mt8192-scp_adsp
20 - mediatek,mt8192-imp_iic_wrap_c
21 - mediatek,mt8192-imp_iic_wrap_e
22 - mediatek,mt8192-imp_iic_wrap_s
23 - mediatek,mt8192-imp_iic_wrap_ws
24 - mediatek,mt8192-imp_iic_wrap_w
25 - mediatek,mt8192-imp_iic_wrap_n
26 - mediatek,mt8192-msdc_top
27 - mediatek,mt8192-mfgcfg
28 - mediatek,mt8192-imgsys
29 - mediatek,mt8192-imgsys2
30 - mediatek,mt8192-vdecsys_soc
31 - mediatek,mt8192-vdecsys
32 - mediatek,mt8192-vencsys
33 - mediatek,mt8192-camsys
34 - mediatek,mt8192-camsys_rawa
35 - mediatek,mt8192-camsys_rawb
36 - mediatek,mt8192-camsys_rawc
37 - mediatek,mt8192-ipesys
38 - mediatek,mt8192-mdpsys
43 '#clock-cells':
47 - compatible
48 - reg
53 - |
54 scp_adsp: clock-controller@10720000 {
55 compatible = "mediatek,mt8192-scp_adsp";
57 #clock-cells = <1>;
60 - |
61 imp_iic_wrap_c: clock-controller@11007000 {
62 compatible = "mediatek,mt8192-imp_iic_wrap_c";
64 #clock-cells = <1>;
67 - |
68 imp_iic_wrap_e: clock-controller@11cb1000 {
69 compatible = "mediatek,mt8192-imp_iic_wrap_e";
71 #clock-cells = <1>;
74 - |
75 imp_iic_wrap_s: clock-controller@11d03000 {
76 compatible = "mediatek,mt8192-imp_iic_wrap_s";
78 #clock-cells = <1>;
81 - |
82 imp_iic_wrap_ws: clock-controller@11d23000 {
83 compatible = "mediatek,mt8192-imp_iic_wrap_ws";
85 #clock-cells = <1>;
88 - |
89 imp_iic_wrap_w: clock-controller@11e01000 {
90 compatible = "mediatek,mt8192-imp_iic_wrap_w";
92 #clock-cells = <1>;
95 - |
96 imp_iic_wrap_n: clock-controller@11f02000 {
97 compatible = "mediatek,mt8192-imp_iic_wrap_n";
99 #clock-cells = <1>;
102 - |
103 msdc_top: clock-controller@11f10000 {
104 compatible = "mediatek,mt8192-msdc_top";
106 #clock-cells = <1>;
109 - |
110 mfgcfg: clock-controller@13fbf000 {
111 compatible = "mediatek,mt8192-mfgcfg";
113 #clock-cells = <1>;
116 - |
117 imgsys: clock-controller@15020000 {
118 compatible = "mediatek,mt8192-imgsys";
120 #clock-cells = <1>;
123 - |
124 imgsys2: clock-controller@15820000 {
125 compatible = "mediatek,mt8192-imgsys2";
127 #clock-cells = <1>;
130 - |
131 vdecsys_soc: clock-controller@1600f000 {
132 compatible = "mediatek,mt8192-vdecsys_soc";
134 #clock-cells = <1>;
137 - |
138 vdecsys: clock-controller@1602f000 {
139 compatible = "mediatek,mt8192-vdecsys";
141 #clock-cells = <1>;
144 - |
145 vencsys: clock-controller@17000000 {
146 compatible = "mediatek,mt8192-vencsys";
148 #clock-cells = <1>;
151 - |
152 camsys: clock-controller@1a000000 {
153 compatible = "mediatek,mt8192-camsys";
155 #clock-cells = <1>;
158 - |
159 camsys_rawa: clock-controller@1a04f000 {
160 compatible = "mediatek,mt8192-camsys_rawa";
162 #clock-cells = <1>;
165 - |
166 camsys_rawb: clock-controller@1a06f000 {
167 compatible = "mediatek,mt8192-camsys_rawb";
169 #clock-cells = <1>;
172 - |
173 camsys_rawc: clock-controller@1a08f000 {
174 compatible = "mediatek,mt8192-camsys_rawc";
176 #clock-cells = <1>;
179 - |
180 ipesys: clock-controller@1b000000 {
181 compatible = "mediatek,mt8192-ipesys";
183 #clock-cells = <1>;
186 - |
187 mdpsys: clock-controller@1f000000 {
188 compatible = "mediatek,mt8192-mdpsys";
190 #clock-cells = <1>;