Lines Matching +full:power +full:-
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/fsl,imx8-acm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shengjiu Wang <shengjiu.wang@nxp.com>
19 - fsl,imx8dxl-acm
20 - fsl,imx8qm-acm
21 - fsl,imx8qxp-acm
26 power-domains:
30 '#clock-cells':
34 ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8-clock.h
41 clock-names:
46 - compatible
47 - reg
48 - power-domains
49 - '#clock-cells'
50 - clocks
51 - clock-names
54 - if:
59 - fsl,imx8qxp-acm
62 power-domains:
64 - description: power domain of IMX_SC_R_AUDIO_CLK_0
65 - description: power domain of IMX_SC_R_AUDIO_CLK_1
66 - description: power domain of IMX_SC_R_MCLK_OUT_0
67 - description: power domain of IMX_SC_R_MCLK_OUT_1
68 - description: power domain of IMX_SC_R_AUDIO_PLL_0
69 - description: power domain of IMX_SC_R_AUDIO_PLL_1
70 - description: power domain of IMX_SC_R_ASRC_0
71 - description: power domain of IMX_SC_R_ASRC_1
72 - description: power domain of IMX_SC_R_ESAI_0
73 - description: power domain of IMX_SC_R_SAI_0
74 - description: power domain of IMX_SC_R_SAI_1
75 - description: power domain of IMX_SC_R_SAI_2
76 - description: power domain of IMX_SC_R_SAI_3
77 - description: power domain of IMX_SC_R_SAI_4
78 - description: power domain of IMX_SC_R_SAI_5
79 - description: power domain of IMX_SC_R_SPDIF_0
80 - description: power domain of IMX_SC_R_MQS_0
86 clock-names:
88 - const: aud_rec_clk0_lpcg_clk
89 - const: aud_rec_clk1_lpcg_clk
90 - const: aud_pll_div_clk0_lpcg_clk
91 - const: aud_pll_div_clk1_lpcg_clk
92 - const: ext_aud_mclk0
93 - const: ext_aud_mclk1
94 - const: esai0_rx_clk
95 - const: esai0_rx_hf_clk
96 - const: esai0_tx_clk
97 - const: esai0_tx_hf_clk
98 - const: spdif0_rx
99 - const: sai0_rx_bclk
100 - const: sai0_tx_bclk
101 - const: sai1_rx_bclk
102 - const: sai1_tx_bclk
103 - const: sai2_rx_bclk
104 - const: sai3_rx_bclk
105 - const: sai4_rx_bclk
107 - if:
112 - fsl,imx8qm-acm
115 power-domains:
117 - description: power domain of IMX_SC_R_AUDIO_CLK_0
118 - description: power domain of IMX_SC_R_AUDIO_CLK_1
119 - description: power domain of IMX_SC_R_MCLK_OUT_0
120 - description: power domain of IMX_SC_R_MCLK_OUT_1
121 - description: power domain of IMX_SC_R_AUDIO_PLL_0
122 - description: power domain of IMX_SC_R_AUDIO_PLL_1
123 - description: power domain of IMX_SC_R_ASRC_0
124 - description: power domain of IMX_SC_R_ASRC_1
125 - description: power domain of IMX_SC_R_ESAI_0
126 - description: power domain of IMX_SC_R_ESAI_1
127 - description: power domain of IMX_SC_R_SAI_0
128 - description: power domain of IMX_SC_R_SAI_1
129 - description: power domain of IMX_SC_R_SAI_2
130 - description: power domain of IMX_SC_R_SAI_3
131 - description: power domain of IMX_SC_R_SAI_4
132 - description: power domain of IMX_SC_R_SAI_5
133 - description: power domain of IMX_SC_R_SAI_6
134 - description: power domain of IMX_SC_R_SAI_7
135 - description: power domain of IMX_SC_R_SPDIF_0
136 - description: power domain of IMX_SC_R_SPDIF_1
137 - description: power domain of IMX_SC_R_MQS_0
143 clock-names:
145 - const: aud_rec_clk0_lpcg_clk
146 - const: aud_rec_clk1_lpcg_clk
147 - const: aud_pll_div_clk0_lpcg_clk
148 - const: aud_pll_div_clk1_lpcg_clk
149 - const: mlb_clk
150 - const: hdmi_rx_mclk
151 - const: ext_aud_mclk0
152 - const: ext_aud_mclk1
153 - const: esai0_rx_clk
154 - const: esai0_rx_hf_clk
155 - const: esai0_tx_clk
156 - const: esai0_tx_hf_clk
157 - const: esai1_rx_clk
158 - const: esai1_rx_hf_clk
159 - const: esai1_tx_clk
160 - const: esai1_tx_hf_clk
161 - const: spdif0_rx
162 - const: spdif1_rx
163 - const: sai0_rx_bclk
164 - const: sai0_tx_bclk
165 - const: sai1_rx_bclk
166 - const: sai1_tx_bclk
167 - const: sai2_rx_bclk
168 - const: sai3_rx_bclk
169 - const: sai4_rx_bclk
170 - const: sai5_tx_bclk
171 - const: sai6_rx_bclk
173 - if:
178 - fsl,imx8dxl-acm
181 power-domains:
183 - description: power domain of IMX_SC_R_AUDIO_CLK_0
184 - description: power domain of IMX_SC_R_AUDIO_CLK_1
185 - description: power domain of IMX_SC_R_MCLK_OUT_0
186 - description: power domain of IMX_SC_R_MCLK_OUT_1
187 - description: power domain of IMX_SC_R_AUDIO_PLL_0
188 - description: power domain of IMX_SC_R_AUDIO_PLL_1
189 - description: power domain of IMX_SC_R_ASRC_0
190 - description: power domain of IMX_SC_R_SAI_0
191 - description: power domain of IMX_SC_R_SAI_1
192 - description: power domain of IMX_SC_R_SAI_2
193 - description: power domain of IMX_SC_R_SAI_3
194 - description: power domain of IMX_SC_R_SPDIF_0
195 - description: power domain of IMX_SC_R_MQS_0
201 clock-names:
203 - const: aud_rec_clk0_lpcg_clk
204 - const: aud_rec_clk1_lpcg_clk
205 - const: aud_pll_div_clk0_lpcg_clk
206 - const: aud_pll_div_clk1_lpcg_clk
207 - const: ext_aud_mclk0
208 - const: ext_aud_mclk1
209 - const: spdif0_rx
210 - const: sai0_rx_bclk
211 - const: sai0_tx_bclk
212 - const: sai1_rx_bclk
213 - const: sai1_tx_bclk
214 - const: sai2_rx_bclk
215 - const: sai3_rx_bclk
221 - |
222 #include <dt-bindings/clock/imx8-lpcg.h>
223 #include <dt-bindings/firmware/imx/rsrc.h>
225 clock-controller@59e00000 {
226 compatible = "fsl,imx8qxp-acm";
228 #clock-cells = <1>;
229 power-domains = <&pd IMX_SC_R_AUDIO_CLK_0>,
264 clock-names = "aud_rec_clk0_lpcg_clk",