Lines Matching +full:bt1 +full:- +full:ccu +full:- +full:pll
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-div.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 Clock Control Unit Dividers
11 - Serge Semin <fancer.lancer@gmail.com>
14 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
15 responsible for the chip subsystems clocking and resetting. The CCU is
18 IP-blocks or to groups of blocks (clock domains). The transformation is done
19 by means of an embedded into CCU PLLs and gateable/non-gateable dividers. The
22 registers. Baikal-T1 CCU is logically divided into the next components:
24 in general can provide any frequency supported by the CCU PLLs).
26 3) AXI-bus clock dividers (AXI) - described in this binding file.
27 4) System devices reference clock dividers (SYS) - described in this binding
31 +---------------+
32 | Baikal-T1 CCU |
33 | +----+------|- MIPS P5600 cores
34 | +-|PLLs|------|- DDR controller
35 | | +----+ |
36 +----+ | | | | |
37 |XTAL|--|-+ | | +---+-|
38 +----+ | | | +-|AXI|-|- AXI-bus
39 | | | +---+-|
41 | | +----+---+-|- APB-bus
42 | +-------|SYS|-|- Low-speed Devices
43 | +---+-|- High-speed Devices
44 +---------------+
46 Each sub-block is represented as a separate DT node and has an individual
50 output is primarily connected to a set of CCU PLLs. Some of PLLs CLKOUT are
51 then passed over CCU dividers to create signals required for the target clock
52 domain (like AXI-bus or System Device consumers). The dividers have the
55 +--------------+
56 CLKIN --|->+----+ 1|\ |
57 SETCLK--|--|/DIV|->| | |
58 CLKDIV--|--| | | |-|->CLKLOUT
59 LOCK----|--+----+ | | |
62 EN------|-----------+ |
63 RST-----|--------------|->RSTOUT
64 +--------------+
66 where CLKIN is the reference clock coming either from CCU PLLs or from an
67 external clock oscillator, SETCLK - a command to update the output clock in
68 accordance with a set divider, CLKDIV - clocks divider, LOCK - a signal of
69 the output clock stabilization, EN - enable/disable the divider block,
70 RST/RSTOUT - reset clocks domain signal. Depending on the consumer IP-core
77 devices, are united into a single clocks provider called System Devices CCU.
78 Similarly the dividers with output clocks utilized as AXI-bus reference clocks
79 are called AXI-bus CCU. Both of them use the common clock bindings with no
81 in the files: 'include/dt-bindings/clock/bt1-ccu.h' and
82 'include/dt-bindings/reset/bt1-ccu.h'. Since System Devices and AXI-bus CCU
83 are a part of the Baikal-T1 SoC System Controller their DT nodes are supposed
90 const: baikal,bt1-ccu-axi
96 - description: CCU SATA PLL output clock
97 - description: CCU PCIe PLL output clock
98 - description: CCU Ethernet PLL output clock
100 clock-names:
102 - const: sata_clk
103 - const: pcie_clk
104 - const: eth_clk
110 - description: External reference clock
111 - description: CCU SATA PLL output clock
112 - description: CCU PCIe PLL output clock
113 - description: CCU Ethernet PLL output clock
115 clock-names:
117 - const: ref_clk
118 - const: sata_clk
119 - const: pcie_clk
120 - const: eth_clk
125 - baikal,bt1-ccu-axi
126 - baikal,bt1-ccu-sys
131 "#clock-cells":
134 "#reset-cells":
141 clock-names:
148 - compatible
149 - "#clock-cells"
150 - clocks
151 - clock-names
154 # AXI-bus Clock Control Unit node:
155 - |
156 #include <dt-bindings/clock/bt1-ccu.h>
158 clock-controller@1f04d030 {
159 compatible = "baikal,bt1-ccu-axi";
161 #clock-cells = <1>;
162 #reset-cells = <1>;
167 clock-names = "sata_clk", "pcie_clk", "eth_clk";
170 - |
171 #include <dt-bindings/clock/bt1-ccu.h>
173 clock-controller@1f04d060 {
174 compatible = "baikal,bt1-ccu-sys";
176 #clock-cells = <1>;
177 #reset-cells = <1>;
183 clock-names = "ref_clk", "sata_clk", "pcie_clk",
186 # Required Clock Control Unit PLL node:
187 - |
188 ccu_pll: clock-controller@1f04d000 {
189 compatible = "baikal,bt1-ccu-pll";
191 #clock-cells = <1>;
194 clock-names = "ref_clk";