Lines Matching +full:tbg +full:- +full:a +full:- +full:s
12 The following is a list of provided IDs for Armada 3700 North bridge clocks:
14 -----------------------------------
33 The following is a list of provided IDs for Armada 3700 South bridge clocks:
35 -----------------------------------
36 0 gbe-50 50 MHz parent clock for Gigabit Ethernet
37 1 gbe-core parent clock for Gigabit Ethernet core
38 2 gbe-125 125 MHz parent clock for Gigabit Ethernet
39 3 gbe1-50 50 MHz clock for Gigabit Ethernet port 1
40 4 gbe0-50 50 MHz clock for Gigabit Ethernet port 0
41 5 gbe1-125 125 MHz clock for Gigabit Ethernet port 1
42 6 gbe0-125 125 MHz clock for Gigabit Ethernet port 0
43 7 gbe1-core Gigabit Ethernet core port 1
44 8 gbe0-core Gigabit Ethernet core port 0
45 9 gbe-bm Gigabit Ethernet Buffer Manager
47 11 usb32-sub2-sys USB 2 clock
48 12 usb32-ss-sys USB 3 clock
53 - compatible : shall be "marvell,armada-3700-periph-clock-nb" for the
55 "marvell,armada-3700-periph-clock-sb" for the south bridge block
56 - reg : must be the register address of North/South Bridge Clock register
57 - #clock-cells : from common clock binding; shall be set to 1
59 - clocks : list of the parent clock phandle in the following order:
60 TBG-A P, TBG-B P, TBG-A S, TBG-B S and finally the xtal clock.
65 nb_perih_clk: nb-periph-clk@13000{
66 compatible = "marvell,armada-3700-periph-clock-nb";
68 clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
69 <&tbg 3>, <&xtalclk>;
70 #clock-cells = <1>;