Lines Matching +full:reset +full:- +full:mask
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/bus/ti-sysc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
16 is mostly used for interaction between module and Power, Reset and Clock
31 pattern: "^target-module(@[0-9a-f]+)?$"
35 - items:
36 - enum:
37 - ti,sysc-omap2
38 - ti,sysc-omap4
39 - ti,sysc-omap4-simple
40 - ti,sysc-omap2-timer
41 - ti,sysc-omap4-timer
42 - ti,sysc-omap3430-sr
43 - ti,sysc-omap3630-sr
44 - ti,sysc-omap4-sr
45 - ti,sysc-omap3-sham
46 - ti,sysc-omap-aes
47 - ti,sysc-mcasp
48 - ti,sysc-dra7-mcasp
49 - ti,sysc-usb-host-fs
50 - ti,sysc-dra7-mcan
51 - ti,sysc-pruss
52 - const: ti,sysc
53 - items:
54 - const: ti,sysc
64 reg-names:
69 - minItems: 1
71 - const: rev
72 - const: sysc
73 - const: syss
74 - items:
75 - const: rev
76 - const: syss
77 - enum: [ sysc, syss ]
79 power-domains:
92 clock-names:
97 - enum: [ ick, fck, sys_clk ]
98 - items:
99 - const: fck
100 - enum: [ ick, dbclk, osc, sys_clk, dss_clk, ahclkx ]
101 - items:
102 - const: fck
103 - const: phy-clk
104 - const: phy-clk-div
105 - items:
106 - const: fck
107 - const: hdmi_clk
108 - const: sys_clk
109 - const: tv_clk
110 - items:
111 - const: fck
112 - const: ahclkx
113 - const: ahclkr
117 Target module reset bit in the RSTCTRL register if wired for the module.
118 Note that the other reset bits should be mapped for the child device
122 reset-names:
124 Target module reset names in the RSTCTRL register, typically named
125 "rstctrl" if only one reset bit is wired for the module.
127 - const: rstctrl
129 '#address-cells':
132 '#size-cells':
137 dma-ranges: true
139 ti,sysc-mask:
140 description: Mask of supported register bits for the SYSCONFIG register
143 ti,sysc-midle:
145 $ref: /schemas/types.yaml#/definitions/uint32-array
147 ti,sysc-sidle:
149 $ref: /schemas/types.yaml#/definitions/uint32-array
151 ti,syss-mask:
152 description: Mask of supported register bits for the SYSSTATUS register
155 ti,sysc-delay-us:
161 ti,no-reset-on-init:
162 description: Interconnect target module shall not be reset at init
165 ti,no-idle-on-init:
169 ti,no-idle:
179 - compatible
180 - '#address-cells'
181 - '#size-cells'
182 - ranges
188 - |
189 #include <dt-bindings/bus/ti-sysc.h>
190 #include <dt-bindings/clock/omap4.h>
192 target-module@2b000 {
193 compatible = "ti,sysc-omap2", "ti,sysc";
198 reg-names = "rev", "sysc", "syss";
200 clock-names = "fck";
201 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
204 ti,sysc-midle = <SYSC_IDLE_FORCE>,
207 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
211 ti,syss-mask = <1>;
212 #address-cells = <1>;
213 #size-cells = <1>;